A high-performance sum of absolute difference implementation for motion estimation

IEEE Transactions on Circuits and Systems for Video Technology

Volumn 16, Issue 7, 2006, Pages 876-883

  Vanne, Jarno ^a   Aho, Eero ^a   Hämäläinen, Timo D ^a   Kuusilinna, Kimmo ^b  

^a TAMPERE UNIVERSITY OF TECHNOLOGY   (Finland)

^b NOKIA RESEARCH CENTER   (United States)

Author keywords

Early termination mechanism; Motion estimation; SAD architecture; Sum of absolute difference (SAD)

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; FORMAL LOGIC; IMAGE CODING; NATURAL FREQUENCIES; OPTIMIZATION;

BLOCK-MATCHING ALGORITHM; EARLY TERMINATION MECHANISM; SAD ARCHITECTURE; SUM OF ABSOLUTE DIFFERENCE (SAD);

MOTION ESTIMATION;

EID: 33746874458     PISSN: 10518215     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSVT.2006.877150     Document Type: Article

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