A 3.2 Gb/s CDR using semi-blind oversampling to achieve high jitter tolerance

IEEE Journal of Solid-State Circuits

Volumn 42, Issue 10, 2007, Pages 2224-2234

  Van Ierssel, Marcus ^a,b   Sheikholeslami, Ali ^a,b   Tamura, Hirotaka ^a,c   Walker, William W ^a,d  

^a IEEE

^b UNIVERSITY OF TORONTO   (Canada)

^c FUJITSU LABORATORIES LTD   (Japan)

^d FUJITSU LABORATORIES OF AMERICA   (United States)

Author keywords

Blind oversampling; Clock and data recovery (CDR); Jitter tolerance; Oversampling; Phase tracking

Indexed keywords

BANDWIDTH; CMOS INTEGRATED CIRCUITS; MICROPROCESSOR CHIPS; NATURAL FREQUENCIES;

CLOCK AND DATA RECOVERY (CDR); HIGH JITTER TOLERANCE; PHASE-TRACKING CDR; SEMI-BLIND OVERSAMPLING;

JITTER;

EID: 34748912291     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2007.905233     Document Type: Conference Paper

References (10)

1. M. Kokubo et al., "Spread-Spectrum clock generator for serial ATA using fractional PLL controlled by AE modulator with level shifter," in IEEE ISSCC 2005 Dig. Tech. Papers, Feb. 2005, pp. 160-161.
2. M. Hsieh and G. Sobelman, "Clock and data recovery with adaptive loop gain for spread spectrum serdes applications," in Proc. IEEE ISCAS 2005, May 2005, pp. 4883-4886.
3. L. M. DeVito, "A versatile clock recovery architecture and monolithic implementation," in Monolothic Phase-Locked Loops and Clock Recovery Circuits, B. Razavi, Ed. New York: IEEE Press, 1996, pp. 405-430.
4. B. Razavi, Monolithic Phase-Locked Loops and Clock Recovery Circuits. New York: IEEE Press, 1996.
5. T. Lee and J. Bulzacchelli, "A 155-MHz clock recovery delay- and phase-locked loop," IEEE J. Solid-State Circuits, vol. 27, no. 12, pp. 1736-1746, Dec. 1992.
6. J. Kim and D. K. Jeong, "Multi-gigabit-rate clock and data recovery based on blind oversampling," IEEE Commun., pp. 68-74, Dec. 2003.
7. M. van Ierssel, A. Sheikholeslami, H. Tamura, and W. W. Walker, "A 3.2 Gb/s semi-blind-oversampling CDR," in IEEE ISSCC 2006 Dig. Tech. Papers, Feb. 2006, pp. 334-335.
8. D. Johns and K. Martin, Analog Integrated Circuit Design. New York: Wiley, 1997.
9. L. Sun et al., "A 1.25-GHz 0.35-μm monolithic CMOS PLL based on a multiphase ring oscillator," IEEE J. Solid-State Circuits, vol. 36, no. 6, pp. 910-916, Jun. 2001.
10. F. Lai and W. Hwang, "Design and implementation of differential cas-code voltage switch with pass-gate (DCVSPG) logic for high-performance digital systems," IEEE J. Solid-State Circuits, vol. 32, no. 4, pp. 563-573, Apr. 1997.