Spread-spectrum clock generator for serial ATA using fractional PLL controlled by ΔΣ modulator with level shifter

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 48, Issue , 2005, Pages

  Kokubo, Masaru ^a   Kawamoto, Takashi ^a   Oshima, Takashi ^a   Noto, Takayuki ^b   Suzuki, Masato ^b   Suzuki, Shigeyuki ^b   Hayasaka, Takashi ^b   Takahashi, Tomoaki ^b   Kasai, Jun ^b  

^a Hitachi ^*  (Japan)

^b RENESAS TECHNOLOGY CORP   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 28144454995     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. Serial ATA Workgroup, "SATA: High Speed Serialized AT Attachment," Rev. 1, Aug., 2001.
2. H. S. Li, Y. C. Cheng and D. Puar, "Dual-Loop Spread-Spectrum Clock Generator," ISSCC Dig. Tech. Papers, vol. 42, pp. 184-185, Feb., 1999.
3. M. Aoyama et al., "3Gb/s, 5000ppm Spread Spectrum SerDes PHY with Frequency Tracking Phase Interpolator for Serial ATA," Symp. VLSI Circuits, pp. 107-110, June, 2003.
4. H. W. Chen and J. C. Wu, "A Spread Spectrum Clock Generator for EMI Reduction," IEICE Trans. Electron., vol. E84-C, no. 12, pp. 1959-1966, Dec., 2001.
5. J.-Y. Michel and C. Neron, "A Frequency Modulated PLL for EMI Reduction in Embedded Application," IEEE ASIC/SOC, vol. 12, pp. 362-365, Sept., 1999.
6. M. Kokubo et al., "Low Supply Voltage and Low-Power 1-GHz PLL Frequency Synthesizer for Mobile Terminals," IEICE Trans. Electron., vol. E86-C, no. 1, pp. 71-78, Jan., 2003.