Clock and data recovery with adaptive loop gain for spread spectrum serdes applications

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2005, Pages 4883-4886

  Hsieh, Ming Ta ^a   Sobelman, Gerald E ^a  

^a University of Minnesota   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADAPTIVE LOOPS; AT ATTACHMENTS; CLOCK AND DATA RECOVERY; CLOCK RATE; DETERMINISTIC JITTER; DIFFERENTIATOR; DIGITAL CMOS; HALF-RATE; PHASE DETECTORS; PHASE INTERPOLATOR; PHASE-SHIFTING; SPECTRERF; SPREAD SPECTRA; SYSTEM OPERATION; VERILOG-A;

ANTENNA PHASED ARRAYS; SPECTRUM ANALYSIS; TIMING JITTER;

CLOCKS;

EID: 34748876104     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2005.1465727     Document Type: Conference Paper

References (4)

1. B. Razavi, "Challenges in the Design of High-Speed Clock Data Recovery Circuit," IEEE Communication Magazine, August 2002, pp 94-101.
2. Serial ATA Working Group, "Serial ATA II: Electrical Specification, Revision 1.0", Serial ATA Working Group http://www. sata-io.org, May 2004.
3. A. Rezayee, and K. Martin, "A 9-16Gb/s Clock and Data Recovery Circuit with Threestate Phase Detector and Dual-Path Loop Architecture," Proceedings of the 2003 European Solid-State Circuits Conference, Estoril, Portugal, pp. 683-686.
4. R. Kreienkamp, U. Langmann, C. Zimmermann, T. Aoyama, "A 10-Gb/s CMOS clock and data recovery circuit with an analog phase interpolator," Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, pp. 73-76.