Post-Layout Leakage Power Minimization Based on Distributed Sleep Transistor Insertion

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn 2004-January, Issue January, 2004, Pages 138-143

  Babighian, Pietro ^a   Benini, Luca ^b   Macii, Alberto ^a   Macii, Enrico ^a  

^a POLITECNICO DI TORINO   (Italy)

^b UNIVERSITY OF BOLOGNA   (Italy)

Author keywords

Leakage Power; Sleep Transistor; Sub Threshold Current

Indexed keywords

CMOS INTEGRATED CIRCUITS; INTEGRATED CIRCUIT LAYOUT; LEAKAGE CURRENTS; LOW POWER ELECTRONICS; POWER ELECTRONICS; SLEEP RESEARCH;

COMMERCIAL TOOLS; FULLY COMPATIBLE; INNOVATIVE ALGORITHMS; LEAKAGE POWER; LEAKAGE POWER REDUCTION; SLEEP TRANSISTORS; SUB-THRESHOLD CURRENT; SUB-THRESHOLD LEAKAGE;

TRANSISTORS;

EID: 84932128231     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/LPE.2004.240853     Document Type: Conference Paper

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