Circuit optimization for leakage power reduction using multi-threshold voltages for high performance microprocessors

Proceedings of the International Symposium on Physical Design

Volumn , Issue , 2007, Pages 67-74

  Shah, Jeegar Tilak ^a   Evers, Marius ^a   Trull, Jeff ^b   Halbutogullari, Alper ^a  

^a ADVANCED MICRO DEVICES   (United States)

^b NONE

Author keywords

EDA; Leakage power; Low power design; Microprocessor; Multi V(TH); Optimization; Sizing; Timing

Indexed keywords

HEURISTIC ALGORITHMS; LEAKAGE CURRENTS; MICROPROCESSOR CHIPS; OPTIMIZATION; THRESHOLD VOLTAGE; TRANSISTORS;

HIGH PERFORMANCE MICROPROCESSORS; LEAKAGE POWER; LOW-POWER DESIGN; MULTI-V(TH);

NETWORKS (CIRCUITS);

EID: 34748893088     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1231996.1232010     Document Type: Conference Paper

References (12)

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