Efficient message passing architecture for high throughput LDPC decoder

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2007, Pages 917-920

  Cui, Zhiqiang ^a   Wang, Zhongfeng ^a  

^a Oregon State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; COMPUTER SIMULATION; DIGITAL ARITHMETIC; MESSAGE PASSING; NETWORK ARCHITECTURE; ROUTING ALGORITHMS;

LDPC DECODERS; PERMUTATION MATRICES; ROUTING COMPLEXITY;

DECODING;

EID: 34548853171     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/iscas.2007.378075     Document Type: Conference Paper

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