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Volumn 2005, Issue , 2005, Pages

Effects of parameter variations on timing characteristics of clocked registers

Author keywords

[No Author keywords available]

Indexed keywords

CLOCKED REGISTERS; DATA PROPAGATION DELAY; PARAMETER VARIATIONS;

EID: 33947120583     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (4)

References (12)
  • 6
    • 0034264975 scopus 로고    scopus 로고
    • Delay and Noise Estimation of CMOS Logic Gates Driving Coupled RC Interconnections
    • September
    • K. T. Tang and E. G. Friedman, "Delay and Noise Estimation of CMOS Logic Gates Driving Coupled RC Interconnections," Integration, the VLSI Journal, Vol. 29, No. 2, pp. 131-165, September 2000.
    • (2000) Integration, the VLSI Journal , vol.29 , Issue.2 , pp. 131-165
    • Tang, K.T.1    Friedman, E.G.2
  • 7
    • 0028547660 scopus 로고
    • Device Parameter Changes Caused by Manufacturing Fluctuations of Deep Submicron MOSFET's
    • November
    • R. Sitte, S. Dimitrijev, and H. B. Harrison, "Device Parameter Changes Caused by Manufacturing Fluctuations of Deep Submicron MOSFET's," IEEE Transactions on Electron Devices, Vol. 41, No. 11, pp. 2210-2215, November 1994.
    • (1994) IEEE Transactions on Electron Devices , vol.41 , Issue.11 , pp. 2210-2215
    • Sitte, R.1    Dimitrijev, S.2    Harrison, H.B.3
  • 8
    • 0033116422 scopus 로고    scopus 로고
    • Comparative Analysis of Master-Slave Latches and Flip-Flops for High-Performance and Low-Power Systems
    • April
    • Vladimir Stojanovic and Vojin G. Oklobdzija, "Comparative Analysis of Master-Slave Latches and Flip-Flops for High-Performance and Low-Power Systems," IEEE Journal of Solid State. Circuits, Vol. 34, No. 4, pp. 536-548, April 1999.
    • (1999) IEEE Journal of Solid State. Circuits , vol.34 , Issue.4 , pp. 536-548
    • Stojanovic, V.1    Oklobdzija, V.G.2
  • 10
    • 0030828211 scopus 로고    scopus 로고
    • New Single-Clock CMOS Latches and Flipflops with Improved Speed and Power Savings
    • January
    • Jiren Yuan and Christer Svensson, "New Single-Clock CMOS Latches and Flipflops with Improved Speed and Power Savings," IEEE Journal of Solid State Circuits, Vol. 32, No. 1, pp. 62-69, January 1997.
    • (1997) IEEE Journal of Solid State Circuits , vol.32 , Issue.1 , pp. 62-69
    • Yuan, J.1    Svensson, C.2
  • 12
    • 0003552056 scopus 로고    scopus 로고
    • The National Technology Roadmap for Semiconductors
    • Technical Report, Semiconductor Industry Association
    • S. I. A., "The National Technology Roadmap for Semiconductors," Technical Report, Semiconductor Industry Association, 2003.
    • (2003)
    • A., S.I.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.