Efficient highly-parallel decoder architecture for quasi-cyclic low-density parity-check codes

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2007, Pages 1855-1858

  Oh, Daesun ^a   Parhi, Keshab K ^a  

^a University of Minnesota   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC POWER UTILIZATION; PARALLEL ALGORITHMS; RESOURCE ALLOCATION; THROUGHPUT;

HARDWARE COMPLEXITY; HARDWARE UTILIZATION EFFICIENCY (HUE); LOW DENSITY PARITY CHECK CODES; PARALLEL DECODER ARCHITECTURE;

DECODING;

EID: 34548839404     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/iscas.2007.378276     Document Type: Conference Paper

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