Functional verification methodology based on formal interface specification and transactor generation

Proceedings -Design, Automation and Test in Europe, DATE

Volumn 1, Issue , 2006, Pages

  Balarin, Felice ^a   Passerone, Roberto ^b  

^a CADENCE DESIGN SYSTEMS   (United States)

^b UNIVERSITY OF TRENTO   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

CODES (SYMBOLS); FORMAL LOGIC; LOGIC DESIGN; SIGNAL PROCESSING;

FUNCTIONAL VERIFICATION METHODOLOGY; SIGNAL BASED COMMUNICATION; TRANSACTION LEVEL MODELS; TRANSACTOR GENERATION;

INTERFACES (COMPUTER);

EID: 34047134555     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/date.2006.243899     Document Type: Conference Paper

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