Impact of process parameters on circuit performance for the 32 nm technology node

Microelectronic Engineering

Volumn 84, Issue 11, 2007, Pages 2738-2743

  Farcy, A ^a   Gallitre, M ^a,b   Arnal, V ^a   Sellier, M ^a   Guibe, L ^c   Blampey, B ^b   Bermond, C ^b   Flechet B ^b   Torres, J ^a  

^a STMICROELECTRONICS   (France)

^b UNIVERSITÉ DE SAVOIE   (France)

^c NXP SEMICONDUCTORS   (France)

Author keywords

32 nm node; Circuit optimization; Delay; Interconnects; Performance; Propagation

Indexed keywords

ELECTRIC NETWORK ANALYSIS; ELECTROMAGNETISM; OPTICAL INTERCONNECTS; OPTIMIZATION; PARAMETER ESTIMATION; TIME DOMAIN ANALYSIS;

32 NM NODE; CIRCUIT APPLICATIONS; CIRCUIT OPTIMIZATION; PROCESS PARAMETERS;

INTEGRATED CIRCUITS;

EID: 34548826769     PISSN: 01679317     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.mee.2007.05.015     Document Type: Article

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