A novel CLB architecture to detect and correct SEU in LUTs of SRAM-based FPGAs

Proceedings - 2004 IEEE International Conference on Field-Programmable Technology, FPT '04

Volumn , Issue , 2004, Pages 121-128

  Sundar, E Syam ^a   Chandrasekhar, Vikram ^a   Sashikanth, M ^a   Kamakoti, V ^a   Narayanan, Vijaykrishnan ^b  

^a INDIAN INSTITUTE OF TECHNOLOGY MADRAS   (India)

^b PENNSYLVANIA STATE UNIVERSITY   (United States)

Author keywords

Duplication with Comparison (DWC); Field Programmable Gate Arrays; Reliability; Single Event Upset Faults; Testing and Fault Tolerance

Indexed keywords

BOOLEAN FUNCTIONS; COMPUTER ARCHITECTURE; ERROR CORRECTION; FAULT TOLERANT COMPUTER SYSTEMS; REDUNDANCY; RELIABILITY; STATIC RANDOM ACCESS STORAGE;

DUPLICATION WITH COMPARISON (DWC); SINGLE EVENT UPSET FAULTS; TESTING AND FAULT-TOLERANCE; TRIPLE MODULAR REDUNDANCY (TMR);

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 20844449226     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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