Online detection and diagnosis of multiple configuration upsets in LUTs of SRAM-based FPGAs

Proceedings - 19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005

Volumn 2005, Issue , 2005, Pages

  Reddy, E Syam Sundar ^a   Chandrasekhar, Vikram ^a   Sashikanth, M ^a   Kamakoti, V ^a   Vijaykrishnan, N ^b  

^a INDIAN INSTITUTE OF TECHNOLOGY MADRAS   (India)

^b PENNSYLVANIA STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BITS; CONFIGURATION; ONLINE DETECTION; SINGLE EVENT UPSETS(SEUS);

COMPUTER ARCHITECTURE; COMPUTER SCIENCE; ERROR ANALYSIS; ONLINE SYSTEMS; STATIC RANDOM ACCESS STORAGE;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 33746273252     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IPDPS.2005.308     Document Type: Conference Paper

References (6)

1. Virtex-II Platform FPGAs: Complete Data Sheet, DS031(v3.3). Xilinx Product Specification, 2004.
2. M. Abramivici and C. Stroud. BIST Based Test and Diagnosis of FPGA Logic Blocks. IEEE Transactions on VLSI Systems, 9(43): 159 - 172, February 2001.
3. M. Abramovici, J. M. Emmert, and C. E. Stroud. Roving STARs: An Integrated Approach to On-Line Testing, Diagnosis, and Fault Tolerance for FPGAs in Adaptive Computing Systems. Proceedings of the third NASA/DoD Workshop on Evolvable Hardware, pages 73-92, July 2001.
4. W. K. Huang and F. Lombardi. An Approach to Testing Programmable/Configurable Field Programmable Gate Arrays. In the proceedings of the IEEE VLSI Test Symposium, pages 450 - 455, 1996.
5. A. Johnston. Scaling and Technology Issues for Soft Error Rates. 4th Annual Research Conference on Reliability, Stanford University, October 2000.
6. F. Lima, L. Carro, and R. Reis. Designing Fault Tolerant Systems into SRAM-based FPGAs. Proceedings of the Design Automation Conference, pages 650 - 655, June 2003.