Area × delay (A · T) efficient multiplier based on an intermediate hybrid signed-digit (HSD-1) representation

Proceedings - Symposium on Computer Arithmetic

Volumn , Issue , 1999, Pages 216-224

  Lue, Jeng Jong J ^a   Phatak, Dhananjay S ^a  

^a Summit Controls Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

INTERCONNECTION NETWORKS; NUMBER THEORY; TRANSISTORS; TREES (MATHEMATICS); VLSI CIRCUITS;

HYBRID SIGNED DIGIT REPRESENTATION; PARTIAL PRODUCTS;

DIGITAL ARITHMETIC;

EID: 0032667135     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (14)