Signed-weight arithmetic and its application to a field-programmable digital filter architecture

IEICE Transactions on Electronics

Volumn E82-C, Issue 9, 1999, Pages 1687-1696

  Aoki, Takafumi ^a,b   Sawada, Yoshiki ^a   Higuchi, Tatsuo ^a  

^a TOHOKU UNIVERSITY   (Japan)

^b JAPAN SCIENCE AND TECHNOLOGY AGENCY   (Japan)

Author keywords

Computer arithmetic; Digital signal processing; FIR filters; FPGAs; Redundant number systems

Indexed keywords

ALGORITHMS; COMPUTATIONAL COMPLEXITY; DIGITAL SIGNAL PROCESSING; FIELD PROGRAMMABLE GATE ARRAYS; FIR FILTERS;

CONFIGURABLE COUNTER TREE ARCHITECTURE; FIELD PROGRAMMABLE DIGITAL FILTER; SIGNED WEIGHT NUMBER SYSTEMS;

DIGITAL ARITHMETIC;

EID: 0033342253     PISSN: 09168524     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

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