System-level process variation driven throughput analysis for single and multiple voltage-frequency island designs

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2007, Pages 403-408

  Garg, Siddharth ^a   Marculescu, Diana ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; CONSTRAINT THEORY; GRAPH THEORY; MONTE CARLO METHODS; PROBABILISTIC LOGICS; THROUGHPUT; VOLTAGE CONTROL;

SYSTEM-LEVEL PROCESSES; VOLTAGE-FREQUENCY ISLANDS (VFI);

LOGIC DESIGN;

EID: 34548304812     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2007.364625     Document Type: Conference Paper

References (12)

1. A.Devgan and C. Kashyap. Block-based static timing analysis with uncertainty. In Proceedings of ICCAD, 2003.
2. H. Chang and S. Sapatnekar. Statistical timing analysis considering spatial correlations using a single pert-like traversal. In Proceedings of ICCAD, 2003.
3. Y. Zhang, A.J. Strojwas, X. Li and L.T. Pileggi. Correlation-aware statistical timing analysis with non-gaussian delay distributions. In Proceedings of DAC ,2005.
4. M. Orshansky and K.Kuetzer. A general probabilistic framework for worst case timing analysis. In Proceedings of DAC, 2002.
5. D. Ernst, N.S. Kim, S. Das, S. Pant, R. Rao, T. Pham, C. Ziesler, D. Blaauw, T. Austin, K. Flautner and T. Mudge. Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation. In MICRO 36: Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture, 2003.
6. T. Chelcea and S. Nowick. Robust interfaces for mixed-timing systems with application to latency-insensitive protocols. In Proceedings of DAC, 2001.
7. A. Mathur, A. Dasdan and R.K. Gupta. Rate analysis for embedded systems. ACM Transactions on Design Automation of Electronic Systems, 3(3), 1998.
8. L.P. Carloni and A.S. Vincentelli. Performance analysis and optimization of latency insensitive systems. In Proceedings of DAC, 2000.
9. A. Dutta, N. Bhunia, A. Banerjee and K. Roy. A power-aware GALS architecture for real-time algorithm-specific tasks. In Proceedings of ISQED, 2005.
10. R.M. Karp. A characterization of the minimum cycle mean in a digraph. Discrete Math, 23, 1978.
11. D. Marculescu and S. Garg. System level process-driven variability analysis for single and multiple voltage-frequency islands. In Proceedings of ICCAD, 2006.
12. S. Stuijik, M. Gielen and T. Basten. SDF3: SDF for free. In Proceedings of ACSD'06, 2006.