A power-aware GALS architecture for real-time algorithm-specific tasks

Proceedings - International Symposium on Quality Electronic Design, ISQED

Volumn , Issue , 2005, Pages 358-363

  Datta, Animesh ^a   Bhunia, Swarup ^a   Banerjee, Nilanjan ^a   Roy, Kaushik ^a  

^a Purdue University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMMERCIAL APPLICATIONS; GALS ARCHITECTURE; ONLINE TRANSACTION PROCESSING; OPERATING CONDITION; PROCESSING UNITS; PROPOSED ARCHITECTURES; SCALABLE ARCHITECTURES; VOLTAGE-SCALING;

DESIGN; DYNAMIC LOADS;

ALGORITHMS;

EID: 53849090235     PISSN: 19483287     EISSN: 19483295     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2005.12     Document Type: Conference Paper

References (14)

1. K. Roy and S. C. Prasad, Low Power CMOS VLSI Circuit Design, Wiley-Interscience, Feb 2000.
2. T. A. Burd et al., A dynamic voltage scaled microprocessor system, IEEE JSSC, 2000, pp. 1571-1580.
3. G. Magklis et al., Profile-based dynamic voltage and frequency scaling for a multiple clock domain microprocessor, ISCA, 2003, pp. 14-25.
4. J. L. Hennessy and D. A. Patterson, Computer Architecture: A Quantitative Approach, Morgan Kaufmann, 3rd edition, 2003.
5. A. Iyer et al., Power and Performance Evaluation of Globally Asynchronous Locally Synchronous Processors, ISCA, 2002, pp. 652-661.
6. G. Semeraro et al., Energy-Efficient Processor Design Using Multiple Clock Domains with Dynamic Voltage and Frequency Scaling, ISHPC, 2002, pp. 29-40.
7. S. W. Moore et al., Self Calibrating Clocks for Globally Asynchronous Locally Synchronous Circuits, ICCD, 2000, pp. 73-78.
8. P. Dibble, Deadline Scheduling, Embedded Systems Programming, 2001.
9. T. Chelcea et al., A Low-Latency FIFO for Mixed-Clock Systems, IEEE CSWVLSI, 2000, pp. 119-126.
10. D. E. Culler and J. P. Singh, Parallel Computer Architecture: A Hardware/ Software Approach, Morgan Kaufmann, 1999.
11. T. K. K. Kan et al., A 2-V 1.8-GHz Fully Integrated CMOS Dual-Loop Frequency Synthesizer, IEEE JSSC, 2002, pp. 1012-1020.
12. H. Li et al., VSV: L2-Miss-Driven Variable Supply Voltage Scaling for Low-Power, IEEE Micro, 2003, pp. 19-28.
13. G. P. Semeraro et al., Hiding Synchronization Delays in GALS Processor Microarchitecture, ASYNC, 2004, pp. 159-169.
14. D. Brooks et al., Wattch: A Framework for Architectural-level Power analysis and Optimization, ISCA, 2000, pp. 83-94.