RESTA: A robust and extendable symbolic timing analysis tool

Proceedings of the ACM Great Lakes Symposium on VLSI

Volumn , Issue , 2004, Pages 407-412

  Nepal, Kundan ^a   Song, Hui Yuan ^a   Bahar, R Iris ^a   Grodstein, Joel ^b  

^a BROWN UNIVERSITY   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

Decision Diagrams; Input Constraints; Symbolic CAD; Timing Analysis

Indexed keywords

DECISION DIAGRAMS; INPUT CONSTRAINTS; SYMBOLIC CAD; TIMING ANALYSIS;

ALGORITHMS; COMPUTATIONAL METHODS; COMPUTER AIDED DESIGN; COMPUTER SIMULATION; ROBUSTNESS (CONTROL SYSTEMS); TRANSISTORS;

INTEGRATED CIRCUITS;

EID: 2942696821     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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