A verification system for transient response of analog circuits

ACM Transactions on Design Automation of Electronic Systems

Volumn 12, Issue 3, 2007, Pages

  Dastidar, Tathagato Rai ^a,c   Chakrabarti, P P ^b,d  

^a Xaneda Technologies

^b INDIAN INSTITUTE OF TECHNOLOGY   (India)

^c Xaneda Technologies India Pvt Ltd

^d INDIAN INSTITUTE OF TECHNOLOGY   (India)

Author keywords

Ana CTL; Analog circuits; Equivalence checking; Model checking; Query language; Transient response

Indexed keywords

FINITE AUTOMATA; MODEL CHECKING; QUERY LANGUAGES; TRANSIENT ANALYSIS; TREES (MATHEMATICS);

COMPUTATIONAL TREE LOGICS; EQUIVALENCE CHECKING;

ANALOG CIRCUITS;

EID: 34548271444     PISSN: 10844309     EISSN: 15577309     Source Type: Journal    
DOI: 10.1145/1255456.1255468     Document Type: Conference Paper

References (32)

1. ACCELLERA, 2004. Verilog AMS. http://www.eda.org/verilog-ams/.
2. ALLEN, R E. AND HOLBERG, D. R. 1987. CMOS Analog Circuit Design. Oxford University Press.
3. ALUR, R. AND WANG, B.-Y. 1999. Next heuristic for on-the-fly model checking. In Proceedings of the 10th International Conference on Concurrency Theory (CONCUR). 98-113.
4. ALUR, R., HENZINGER, T. A., AND HO, P-H. 1996. Automatic symbolic verification of embedded systems. IEEE Trans. Softw. Eng. 22, 181-201.
5. ALUR, R. AND DILL, D. L. 1994. A theory of timed automata. Theor. Comput. Sci. 126, 183-235.
6. ANALOG INSYDES. 2007. Analog Insydes version 2.1. http://www.analog-inydes.de/.
7. BALIVADA, A., HOSKOTE, Y., AND ABRAHAM, J. A. 1995. Verification of transient response of linear analog circuits. In Proceedings of the 13th IEEE VLSI Test Symposium (VTC). 42-47.
8. BANERJEE, A. AND DASGUPTA, P. 2005. The open family of temporal logics: Annotating temporal operators with input constraints. ACM Trans. Des. Autom. Electron. Syst. 10, 3 (Jul.), 492-522.
9. BEHRMANN, G., LARSEN, K. G., MOLLER, O., DAVID, A., AND PETTERSON, R 2001. UPPAL - Present and future. In Proceedings of the 40th IEEE Conference on Decision and Control. 2881-2886.
10. BIERE, A., CIMATTI, A., CLARKE, E., AND ZHU, Y 1999. Symbolic model checking without BDDs. In Proceedings of the Workshop on Tools and Algorithms for the Construction and Analysis of Systems (TACAS). Springer, 193-207.
11. BURCH, J. R., CLARKE, E. M., LONG, D. E., MCMILLAN, K. L., AND DILL, D. L. 1994. Symbolic model checking for sequential circuit verification. IEEE Trans. Comput. Aided Des. Integr. Circ. Syst. 13, 4 (Apr.), 401-424.
12. CHUTINAN, A. AND KROGH, B. H. 2003. Computational techniques for hybrid system verification. IEEE Trans. Autom. Control 48, 1, 64-75.
13. CLARKE, E. M. JR., GRUMBERG, O., AND PELED, D. A. 2000. Model Checking. MIT Press, Cambridge, MA.
14. CORMEN, T. H., LEISERSON, C E., AND RIVEST, R. E. 1990. Introduction to Algorithms. MIT Press, Cambridge, MA.
15. DANG, T. AND MALER, O. 2000. d/dt: Reachability analysis of continuous and hybrid systems. http://www-verimag.imag. fr/~tdang/ddt.html.
16. DANG, T., DONZE, A., AND MALER, O. 2004. Verification of analog and mixed-signal circuits using hybrid systems techniques. In Proceedings of the International Conference on Formal Methods in Computer-Aided Design (FMCAD) (Nov.).
17. DASGUPTA, P., CHAKRABARTI, A., AND CHAKRABARTI, P. P. 2002. Open computation tree logic for formal verification of modules. In Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC). 735-740.
18. DASTIDAR, T. R. AND CHAKRABARTI, P. P. 2005. A verification system for transient response of analog circuits using model checking. In Proceedings of the 18th International Conference on VLSI Design. 195-200.
19. FREHSE, G., KROGH, B. H., AND RUTENBAR, R. A. 2006. Verifying analog oscillator circuits using forward/backward abstraction refinement. In Proceedings of the Conference and Exhibtion on Design, Automation and Test in Europe (DATE). 257-262.
20. GHOSH, A. AND VEMURI, R. 1999. Formal verification of synthesized analog circuits. In Proceedings of the ACM/IEEE International Conference on Computer Design. 40-45.
21. GUPTA, S., KROGH, B. H., AND RUTENBAR, R. A. 2004. Towards formal verification of analog designs. In Proceedings of the IEEE International Conference on Computer-Aided Design (ICCAD). 210-217.
22. HARTONG, W., HEDRICH, L., AND BARKE, E. 2002a. Model checking algorithms for analog verification. In Proceedings of the IEEE /ACM Design Automation Conference (DAC). 542-547.
23. HARTONG, W., HEDRICH, L., AND BARKE, E. 2002b. On discrete modeling and model checking for nonlinear analog systems. In Proceedings of the 14th International Conference on Computer-Aided Verification. 401-413.
24. HENNIG, E. 2000. Symbolic Approximation and Modeling Techniques for Analysis and Design of Analog Circuits. Shaker, Aachen, Germany.
25. MCCALLA, W. J. 1988. Fundamentals of Computer-Aided Circuits Simulation. Kluwer Academic, Hingham, MA.
26. NUSMV. 2007. NuSMV: A new symbolic model checker. http://nusmv.irst.itc.it/.
27. PHAVER. 2006. PHAVer: Polyhedral hybrid automaton verifyer. http://www.cs.ru.nl/~goranf/.
28. QUARLES, T., PEDERSON, D., NEWTON, R., SANGIOVANNI-VINCENTELLI, A., AND WAYNE, C 2007. The Spice page. http://bwrc.eecs.berkeley.edu/Classes/IcBook/SPICE.
29. QUARLES, T. L. 1989. The Spice3 implementation guide. Memorandum no. UCB/ERL M89/44, College of Engineering, University of California at Berkeley, Berkeley, CA.
30. SANTONE, A. 2003. Heuristic search + local model checking in selective mu-calculus. IEEE Trans. Softw. Eng. 29, 6 (Jun.).
31. SILVA, B. I., STURSBERG, O., KROGH, B. H., AND ENGELL, S. 2001. An assessment of the current status of algorithmic approaches to the verification of hybrid systems. In Proceedings of the 40th IEEE Conference on Decision and Control. 2867-2874.
32. TAN, S. X.-D. AND SHI, C-J. R. 2001. Compact representation and efficient generation of s-expanded symbolic network functions for computer-aided analog circuit design. IEEE Trans. Comput. Aided Des. Integr. Circ. Syst. 20, 7 (Jul.), 813-827.