Symbolic Model Checking for Sequential Circuit Verification

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 13, Issue 4, 1994, Pages 401-424

  Burch, Jerry R ^a   Clarke, Edmund M ^a   Long, David E ^a   McMillan, Kenneth L ^a   Dill, David L ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; APPROXIMATION THEORY; CONTROLLABILITY; DECISION TABLES; DECISION THEORY; DIGITAL CIRCUITS; INTEGRATED CIRCUIT TESTING; MATHEMATICAL MODELS; STATE SPACE METHODS; THEOREM PROVING;

BINARY DECISION DIAGRAMS; PARTITIONED TRANSITION RELATIONS; REACHABILITY ANALYSIS ALGORITHMS; SYMBOLIC MODEL CHECKING; TEMPORAL LOGIC MODEL CHECKING ALGORITHM;

SEQUENTIAL CIRCUITS;

EID: 0028413136     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/43.275352     Document Type: Article

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