Formal verification of synthesized analog designs

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 1999, Pages 40-45

  Ghosh, Abhijit ^a   Vemuri, Ranga ^a  

^a UNIVERSITY OF CINCINNATI   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC NETWORK SYNTHESIS; LINEAR INTEGRATED CIRCUITS; MATHEMATICAL MODELS; PIECEWISE LINEAR TECHNIQUES;

FORMAL VERIFICAITON;

INTEGRATED CIRCUIT LAYOUT;

EID: 0033293455     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (11)