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Volumn , Issue , 2006, Pages

The potential energy efficiency of vector acceleration

Author keywords

[No Author keywords available]

Indexed keywords

DATA CENTER; LOOP KERNELS; MEMORY CHANNELS; UNIPROCESSORS;

EID: 34548226972     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1188455.1188537     Document Type: Conference Paper
Times cited : (10)

References (20)
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    • Cray assembly language (CAL) reference manual
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    • Validity of the single-processor approach to acheiving large-scale computing capability
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    • G. M. Amdahl. Validity of the single-processor approach to acheiving large-scale computing capability. In AFIPS Conference Proceedings, pages 483-485, April 1967.
    • (1967) AFIPS Conference Proceedings , pp. 483-485
    • Amdahl, G.M.1
  • 4
    • 0033719421 scopus 로고    scopus 로고
    • Wattch:a framework for architectural-level power analysis and optimizations
    • Vancouver, Canada, June
    • D. Brooks, V. Tiwari, and M. Martonosi. Wattch:a framework for architectural-level power analysis and optimizations. In Proc. Intl. Symp. on Computer Arch. (ISCA), Vancouver, Canada, June 2000.
    • (2000) Proc. Intl. Symp. on Computer Arch. (ISCA)
    • Brooks, D.1    Tiwari, V.2    Martonosi, M.3
  • 5
    • 84877083867 scopus 로고    scopus 로고
    • Merrimac: Supercomputing with streams
    • Phoenix, AZ, Nov
    • W. J. Dally et al. Merrimac: Supercomputing with streams. In Supercomputing (SC'03), Phoenix, AZ, Nov. 2003.
    • (2003) Supercomputing (SC'03)
    • Dally, W.J.1
  • 6
    • 0036292604 scopus 로고    scopus 로고
    • Tarantula: A vector extension to the Alpha architecture
    • Anchorage, Alaska, June
    • R. Espasa et al. Tarantula: a vector extension to the Alpha architecture. In Proc. Intl. Symp. on Computer Arch. (ISCA), pages 281-294, Anchorage, Alaska, June 2003.
    • (2003) Proc. Intl. Symp. on Computer Arch. (ISCA) , pp. 281-294
    • Espasa, R.1
  • 9
    • 0031069405 scopus 로고    scopus 로고
    • A 600 MHz superscalar RISC microprocessor with out-of-order execution
    • Feb
    • B. A. Gieseke et al. A 600 MHz superscalar RISC microprocessor with out-of-order execution. In Intl Solid-State Circuits Conference (ISSCC'97), pages 176-175, Feb. 1997.
    • (1997) Intl Solid-State Circuits Conference (ISSCC'97) , pp. 176-175
    • Gieseke, B.A.1
  • 10
    • 34547710630 scopus 로고    scopus 로고
    • Fully-buffered dimm technology moves enterprise platforms to the next level
    • Mar
    • J. Haas and P. Vogt. Fully-buffered dimm technology moves enterprise platforms to the next level. Technology at Intel Magazine, pages 1-7, Mar. 2005.
    • (2005) Technology at Intel Magazine , pp. 1-7
    • Haas, J.1    Vogt, P.2
  • 11
    • 84948978169 scopus 로고    scopus 로고
    • Vector vs. superscalar and VLIW architectures for embedded multimedia benchmarks
    • Istanbul, Turkey
    • C. Kozyrakis and D. Patterson. Vector vs. superscalar and VLIW architectures for embedded multimedia benchmarks. In Intl Symp. on Microarchitecture (MICRO), page 283293, Istanbul, Turkey, 2002.
    • (2002) Intl Symp. on Microarchitecture (MICRO) , pp. 283293
    • Kozyrakis, C.1    Patterson, D.2
  • 14
  • 17
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    • Cacti 3.0: An integrated cache timing, power, and area model
    • Report 2001/02, 2001
    • P. Shivakumar and N. P. Jouppi. Cacti 3.0: An integrated cache timing, power, and area model. Technical Report WRL Technical Report 2001/02, 2001.
    • Technical Report WRL Technical
    • Shivakumar, P.1    Jouppi, N.P.2
  • 20
    • 18344379039 scopus 로고    scopus 로고
    • DRAM tuning looks to speed graphics work
    • Apr
    • R. Wilson. DRAM tuning looks to speed graphics work. EE Times, pages 40-44, Apr. 2005.
    • (2005) EE Times , pp. 40-44
    • Wilson, R.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.