메뉴 건너뛰기




Volumn , Issue , 2004, Pages 331-342

Cache refill/access decoupling for vector machines

Author keywords

[No Author keywords available]

Indexed keywords

CACHE REFILL; COMPUTER-INTENSIVE APPLICATIONS; MEMORY LATENCY; VECTOR MACHINES;

EID: 15044356791     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MICRO.2004.9     Document Type: Conference Paper
Times cited : (15)

References (30)
  • 1
    • 84947253476 scopus 로고    scopus 로고
    • So many states, so little time: Verifying memory coherence in the Cray XI
    • Apr
    • D. Abts, S. Scott, and D. J. Lilja. So many states, so little time: Verifying memory coherence in the Cray XI. In IPDPS, Apr 2003.
    • (2003) IPDPS
    • Abts, D.1    Scott, S.2    Lilja, D.J.3
  • 2
    • 33646469146 scopus 로고
    • An effective on-chip preloading scheme to reduce data access penalty
    • J.-L. Baer and T.-F. Chen. An effective on-chip preloading scheme to reduce data access penalty. In ICS, 1991.
    • (1991) ICS
    • Baer, J.-L.1    Chen, T.-F.2
  • 4
    • 84944416023 scopus 로고    scopus 로고
    • The reconfigurable streaming vector processor (RSVP)
    • Dec
    • S. Ciricescu et al. The reconfigurable streaming vector processor (RSVP). In MICRO-36, pages 141-150, Dec 2003.
    • (2003) MICRO-36 , pp. 141-150
    • Ciricescu, S.1
  • 5
    • 21644483642 scopus 로고    scopus 로고
    • Vector and scalar data cache for a vector multiprocessor. U.S. Patent 6,665,774, Dec
    • Cray. Vector and scalar data cache for a vector multiprocessor. U.S. Patent 6,665,774, Dec 2003.
    • (2003)
    • Cray1
  • 7
    • 0030662863 scopus 로고    scopus 로고
    • Improving data cache performance by pre-executing instructions under a cache miss
    • Jul
    • J. Dundas and T. Mudge. Improving data cache performance by pre-executing instructions under a cache miss. In Proc. ICS, pages 68-75, Jul 1997.
    • (1997) Proc. ICS , pp. 68-75
    • Dundas, J.1    Mudge, T.2
  • 8
    • 0036292604 scopus 로고    scopus 로고
    • Tarantula: A vector extension to the Alpha architecture
    • R. Espasa et al. Tarantula: a vector extension to the Alpha architecture. In 1SCA-29, 2002.
    • (2002) 1SCA-29
    • Espasa, R.1
  • 9
    • 0029700927 scopus 로고    scopus 로고
    • Decoupled vector architectures
    • Feb
    • R. Espasa and M. Valero. Decoupled vector architectures. In HPCA-2, Feb 1996.
    • (1996) HPCA-2
    • Espasa, R.1    Valero, M.2
  • 11
    • 0348097872 scopus 로고    scopus 로고
    • A CMOS vector processor with a custom streaming cache
    • Aug
    • G. Faanes. A CMOS vector processor with a custom streaming cache. In Proc. Hot Chips 10, Aug 1998.
    • (1998) Proc. Hot Chips , vol.10
    • Faanes, G.1
  • 12
    • 0026157234 scopus 로고
    • Data prefetching in multiprocessor vector cache memories
    • May
    • J. W. C. Fu and J. H. Patel. Data prefetching in multiprocessor vector cache memories. In ISCA-18, May 1991.
    • (1991) ISCA-18
    • Fu, J.W.C.1    Patel, J.H.2
  • 13
    • 2342652812 scopus 로고    scopus 로고
    • Stream register files with indexed access
    • Feb
    • N. Jayasena et al. Stream register files with indexed access. In HPCA-10, page 60, Feb 2004.
    • (2004) HPCA-10 , pp. 60
    • Jayasena, N.1
  • 14
    • 0025429331 scopus 로고
    • Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers
    • N. P. Jouppi. Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers. In ISCA-17, 1990.
    • (1990) ISCA-17
    • Jouppi, N.P.1
  • 15
    • 0032639289 scopus 로고    scopus 로고
    • The alpha 21264 microprocessor
    • Mar/Apr
    • R. E. Kessler. The Alpha 21264 microprocessor. IEEE Micro, 19(2):24-36, Mar/Apr 1999.
    • (1999) IEEE Micro , vol.19 , Issue.2 , pp. 24-36
    • Kessler, R.E.1
  • 16
    • 0035271572 scopus 로고    scopus 로고
    • Imagine: Media processing with streams
    • Mar/Apr
    • B. Khailany et al. Imagine: Media processing with streams. IEEE Micro, Mar/Apr 2001.
    • (2001) IEEE Micro
    • Khailany, B.1
  • 18
    • 0038684220 scopus 로고    scopus 로고
    • Overcoming the limitations of conventional vector processors
    • Jun
    • C. Kozyrakis and D. Patterson. Overcoming the limitations of conventional vector processors. In ISCA-30, Jun 2003.
    • (2003) ISCA-30
    • Kozyrakis, C.1    Patterson, D.2
  • 19
    • 4644337990 scopus 로고    scopus 로고
    • The vector-thread architecture
    • Jun
    • R. Krashinsky et al. The vector-thread architecture. In JSCA-31, Jun 2004.
    • (2004) JSCA-31
    • Krashinsky, R.1
  • 20
    • 0019892368 scopus 로고
    • Lockup-free instruction fetch/prefetch cache organization
    • May
    • D. Kroft. Lockup-free instruction fetch/prefetch cache organization. In ISCA-8, pages 81-87, May 1981.
    • (1981) ISCA-8 , pp. 81-87
    • Kroft, D.1
  • 21
    • 1342282617 scopus 로고    scopus 로고
    • Runahead execution: An effective alternative to large instruction windows
    • Nov/Dec
    • O. Mutlu et al. Runahead execution: An effective alternative to large instruction windows. IEEE Micro, Nov/Dec 2003.
    • (2003) IEEE Micro
    • Mutlu, O.1
  • 22
    • 0028294834 scopus 로고
    • Evaluating stream buffers as a secondary cache replacement
    • S. Palacharla and R. E. Kessler. Evaluating stream buffers as a secondary cache replacement. In ISCA-21, pages 24-33, 1994.
    • (1994) ISCA-21 , pp. 24-33
    • Palacharla, S.1    Kessler, R.E.2
  • 23
    • 0017922490 scopus 로고
    • The cray-1 computer system
    • Jan
    • R. M. Russel. The Cray-1 Computer System. CACM, 21(1):63-72, Jan 1978.
    • (1978) CACM , vol.21 , Issue.1 , pp. 63-72
    • Russel, R.M.1
  • 24
    • 0030676682 scopus 로고    scopus 로고
    • Data prefetching on the HP PA-8000
    • V. Santhanam, E. H. Gornish, and W.-C. Hsu. Data prefetching on the HP PA-8000. In ISCA-24, pages 264-273, 1997.
    • (1997) ISCA-24 , pp. 264-273
    • Santhanam, V.1    Gornish, E.H.2    Hsu, W.-C.3
  • 25
    • 21644447255 scopus 로고    scopus 로고
    • Supercomputing past, present, and future
    • Jun
    • S. Scott. Supercomputing past, present, and future. ICS-18 Keynote Address, Jun 2004.
    • (2004) ICS-18 Keynote Address
    • Scott, S.1
  • 26
    • 85046463637 scopus 로고
    • Decoupled access/execute computer architecture
    • J. E. Smith. Decoupled access/execute computer architecture. In ISCA-9, 1982.
    • (1982) ISCA-9
    • Smith, J.E.1
  • 27
    • 0024701055 scopus 로고
    • Dynamic instruction scheduling and the Astronautics ZS-1
    • J. E. Smith. Dynamic instruction scheduling and the Astronautics ZS-1. IEEE Computer, 22(7):21-35, 1989.
    • (1989) IEEE Computer , vol.22 , Issue.7 , pp. 21-35
    • Smith, J.E.1
  • 28
    • 0022952846 scopus 로고
    • The IBM 3090 system: An overview
    • S. G. Tucker. The IBM 3090 system: An Overview. IBM Systems Journal, 25(1):4-19, 1986.
    • (1986) IBM Systems Journal , vol.25 , Issue.1 , pp. 4-19
    • Tucker, S.G.1
  • 29
    • 0022750416 scopus 로고
    • Architecture and performance of NEC supercomputer SX system
    • T. Watanabe. Architecture and performance of NEC supercomputer SX system. Parallel Computing, 5:247-255, 1987.
    • (1987) Parallel Computing , vol.5 , pp. 247-255
    • Watanabe, T.1
  • 30
    • 0031190399 scopus 로고    scopus 로고
    • When caches aren't enough: Data prefetching techniques
    • Jul
    • S. P. V. Wiel and D. J. Lilja. When caches aren't enough: Data prefetching techniques. IEEE Computer, 30(7):23-30, Jul 1997.
    • (1997) IEEE Computer , vol.30 , Issue.7 , pp. 23-30
    • Wiel, S.P.V.1    Lilja, D.J.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.