-
1
-
-
84884185725
-
Collaborative operating system and compiler power management for real-time applications
-
ABOUGHAZALEH, N., MOSSÉ, D., CHILDERS, B., MELHEM, R. G., AND CRAVEN, M. 2003. Collaborative operating system and compiler power management for real-time applications. In Proceedings of the IEEE Real Time Technology and Applications Symposium. 133-143.
-
(2003)
Proceedings of the IEEE Real Time Technology and Applications Symposium
, pp. 133-143
-
-
ABOUGHAZALEH, N.1
MOSSÉ, D.2
CHILDERS, B.3
MELHEM, R.G.4
CRAVEN, M.5
-
2
-
-
3042565410
-
Overhead-Conscious voltage selection for dynamic and leakage energy reduction of time-constrained systems
-
ANDREI, A., SCHMITZ, M., ELES, P., PENG, Z., AND AL-HASHIMI, B. M. 2004. Overhead-Conscious voltage selection for dynamic and leakage energy reduction of time-constrained systems. In Proceedings of the Conference on Design, Automation and Test in Europe. 518-523.
-
(2004)
Proceedings of the Conference on Design, Automation and Test in Europe
, pp. 518-523
-
-
ANDREI, A.1
SCHMITZ, M.2
ELES, P.3
PENG, Z.4
AL-HASHIMI, B.M.5
-
3
-
-
84893766434
-
Profile-Based dynamic voltage scheduling using program checkpoints
-
AZEVEDO, A., ISSENIN, I., CORNEA, R., GUPTA, R., DUTT, N., AND VEIDENBAUM, A. 2002. Profile-Based dynamic voltage scheduling using program checkpoints. In Design Automation and Test in Europe. 168-175.
-
(2002)
Design Automation and Test in Europe
, pp. 168-175
-
-
AZEVEDO, A.1
ISSENIN, I.2
CORNEA, R.3
GUPTA, R.4
DUTT, N.5
VEIDENBAUM, A.6
-
4
-
-
34548218157
-
-
BERKELEY-MODEL. http://www-device.eecs.berkeley.edu/ ~ptm/introduction.html.
-
BERKELEY-MODEL. http://www-device.eecs.berkeley.edu/ ~ptm/introduction.html.
-
-
-
-
5
-
-
0034315851
-
-
BURD, T., PERING, T., STRATAKOS, A., AND BRODERSEN, R. 2000. A dynamic voltage scaled microprocessor system. IEEE J. Solid-State Circ. 35, 11 (Nov.), 1571-1580.
-
BURD, T., PERING, T., STRATAKOS, A., AND BRODERSEN, R. 2000. A dynamic voltage scaled microprocessor system. IEEE J. Solid-State Circ. 35, 11 (Nov.), 1571-1580.
-
-
-
-
6
-
-
84962299846
-
-
DUARTE, D., TSAI, Y., VIJAYKRISHNAN, N., AND IRWIN, M. J. 2002. Evaluating run-time techniques for leakage power reduction. In Proceedings of the International Conference on VLSI Design. 31-38.
-
DUARTE, D., TSAI, Y., VIJAYKRISHNAN, N., AND IRWIN, M. J. 2002. Evaluating run-time techniques for leakage power reduction. In Proceedings of the International Conference on VLSI Design. 31-38.
-
-
-
-
7
-
-
0036396948
-
Impact of scaling on the effectiveness of dynamic power reduction schemes
-
DUARTE, D., VIJAYKRISHNAN, N., IRWIN, M. J., KIM, H.-S., AND MCFARLAND, G. 2002. Impact of scaling on the effectiveness of dynamic power reduction schemes. In Proceedings of the International Conference on Computer Design. 382-387.
-
(2002)
Proceedings of the International Conference on Computer Design
, pp. 382-387
-
-
DUARTE, D.1
VIJAYKRISHNAN, N.2
IRWIN, M.J.3
KIM, H.-S.4
MCFARLAND, G.5
-
8
-
-
84962779213
-
Mibench: A free, commercially representative embedded benchmark suite
-
GUTHAUS, M., RINGENBERG, J., ERNST, D., AUSTIN, T., AND MUDGE, T. 2001. Mibench: A free, commercially representative embedded benchmark suite. In Proceedings of the IEEE 4th Annual Workshop on Workload Characterization. 3-14.
-
(2001)
Proceedings of the IEEE 4th Annual Workshop on Workload Characterization
, pp. 3-14
-
-
GUTHAUS, M.1
RINGENBERG, J.2
ERNST, D.3
AUSTIN, T.4
MUDGE, T.5
-
11
-
-
0036858382
-
-
KAO, J., MIYAZAKI, M., AND CHANDRAKASAN, A. 2002. A 175-mv multiply-accumulate unit using an adaptive supply voltage and body bias architecture. J. Solid-State Circu. 37, 11 (Nov.), 1545-1554.
-
KAO, J., MIYAZAKI, M., AND CHANDRAKASAN, A. 2002. A 175-mv multiply-accumulate unit using an adaptive supply voltage and body bias architecture. J. Solid-State Circu. 37, 11 (Nov.), 1545-1554.
-
-
-
-
12
-
-
0033359156
-
Technology scaling behavior of optimum reverse body bias for leakage power reduction in ICS
-
KESHARVARZI, A., NARENDA, S., BORKAR, S., HAWKINS, C., ROY, K., AND DE, V. 1999. Technology scaling behavior of optimum reverse body bias for leakage power reduction in ICS. In Proceedings of the International Symposium Low Power Electronics and Design. 252-254.
-
(1999)
Proceedings of the International Symposium Low Power Electronics and Design
, pp. 252-254
-
-
KESHARVARZI, A.1
NARENDA, S.2
BORKAR, S.3
HAWKINS, C.4
ROY, K.5
DE, V.6
-
14
-
-
22844455988
-
Performance estimation of embedded software with instruction cache modeling
-
LI, Y., MALIK, S., AND WOLFE, A. 1999. Performance estimation of embedded software with instruction cache modeling. ACM Trans. Des. Autom. Electron. Syst. 4, 3, 257-279.
-
(1999)
ACM Trans. Des. Autom. Electron. Syst
, vol.4
, Issue.3
, pp. 257-279
-
-
LI, Y.1
MALIK, S.2
WOLFE, A.3
-
15
-
-
34548286801
-
-
LONGRUN. 2007. http://www.transmeta.com/technology/architecture/ longrun.html.
-
(2007)
-
-
LONGRUN1
-
16
-
-
0036917242
-
Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads
-
MARTIN, S., FLAUTNER, K., MUDGE, T., AND BLAAUW, D. 2002. Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads. In Proceedings of the IEEE/ACM International Conference on Computer-Aided Design. 721-725.
-
(2002)
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design
, pp. 721-725
-
-
MARTIN, S.1
FLAUTNER, K.2
MUDGE, T.3
BLAAUW, D.4
-
19
-
-
84959037266
-
Optimizing static power dissipation by functional units in superscalar processors
-
RELE, S., PANDE, S., ONDER, S., AND GUPTA, R. 2002. Optimizing static power dissipation by functional units in superscalar processors. In Proceedings of the 11th International Conference on Compiler Construction. 261-275.
-
(2002)
Proceedings of the 11th International Conference on Compiler Construction
, pp. 261-275
-
-
RELE, S.1
PANDE, S.2
ONDER, S.3
GUPTA, R.4
-
20
-
-
0004312443
-
An introduction to machine suif and its portable libraries for analysis and optimization
-
Tech. Rep, Division of Engineering and Applied Sciences, Harvard University
-
SMITH, M. AND HOLLOWAY, G. 2002. An introduction to machine suif and its portable libraries for analysis and optimization. Tech. Rep., Division of Engineering and Applied Sciences, Harvard University.
-
(2002)
-
-
SMITH, M.1
HOLLOWAY, G.2
-
21
-
-
34547192335
-
Efficient detection and exploitation of infeasible paths for software timing analysis
-
SUHENDRA, V., MITRA, T., ROYCHOUDHURY, A., AND CHEN, T. 2006. Efficient detection and exploitation of infeasible paths for software timing analysis. In Proceedings of the Design Automation Conference.
-
(2006)
Proceedings of the Design Automation Conference
-
-
SUHENDRA, V.1
MITRA, T.2
ROYCHOUDHURY, A.3
CHEN, T.4
-
22
-
-
84982859985
-
-
XIE, F., MARTONOSI, M., AND MALIK, S. 2004. Intraprogram dynamic voltage scaling: Bounding opportunities with analytic modeling. ACM Trans. Architecture Code Optimization 1, 3 (Sept.), 1-45.
-
XIE, F., MARTONOSI, M., AND MALIK, S. 2004. Intraprogram dynamic voltage scaling: Bounding opportunities with analytic modeling. ACM Trans. Architecture Code Optimization 1, 3 (Sept.), 1-45.
-
-
-
-
23
-
-
34548223567
-
-
XSCALE. 2007. http://www.intel.com/design/intelxscale.
-
(2007)
-
-
XSCALE1
-
26
-
-
33745216419
-
Compilers for leakage power reduction
-
YOU, Y., LEE, C., AND LEE, J. 2006. Compilers for leakage power reduction. ACM Trans. Des. Autom. Electron. Syst. 11, 1, 147-164.
-
(2006)
ACM Trans. Des. Autom. Electron. Syst
, vol.11
, Issue.1
, pp. 147-164
-
-
YOU, Y.1
LEE, C.2
LEE, J.3
-
27
-
-
70350201078
-
Compiler support for reducing leakage energy consumption
-
ZHANG, W., KANDEMIR, M., VIJAYKRISHNAN, N., IRWIN, M., AND DE, V. 2003. Compiler support for reducing leakage energy consumption. In Proceedings of the Design, Automation and Test in Europe Conference and Exhibition. 1146-1147.
-
(2003)
Proceedings of the Design, Automation and Test in Europe Conference and Exhibition
, pp. 1146-1147
-
-
ZHANG, W.1
KANDEMIR, M.2
VIJAYKRISHNAN, N.3
IRWIN, M.4
DE, V.5
|