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Volumn , Issue , 2006, Pages 139-145

Dependable design for FPGA based on duplex system and reconfiguration

Author keywords

[No Author keywords available]

Indexed keywords

FIELD PROGRAMMABLE GATE ARRAYS (FPGA); SYSTEMS ANALYSIS;

EID: 34547998325     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DSD.2006.38     Document Type: Conference Paper
Times cited : (12)

References (17)
  • 3
    • 33847139585 scopus 로고    scopus 로고
    • QuickLogic Corporation
    • QuickLogic Corporation.: Single Event Upsets in FPGAs, 2003, www.quicklogic.com
    • (2003) Single Event Upsets in FPGAs
  • 5
    • 0030349739 scopus 로고    scopus 로고
    • Single Event Upset at Ground Level
    • Normand, E.: "Single Event Upset at Ground Level," IEEE Transactions on Nuclear Science, vol. 43, 1996, pp. 2742-2750.
    • (1996) IEEE Transactions on Nuclear Science , vol.43 , pp. 2742-2750
    • Normand, E.1
  • 11
  • 17
    • 34547987110 scopus 로고    scopus 로고
    • Kubalik, P., Kubatova, H.: High Reliable FPGA Based System Design Methodology. Work in Progress Session of 30th EUROMICRO and DSD 2004, Universitat Linz 2004 pp. 30-31.
    • Kubalik, P., Kubatova, H.: "High Reliable FPGA Based System Design Methodology." Work in Progress Session of 30th EUROMICRO and DSD 2004, Universitat Linz 2004 pp. 30-31.


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.