A design flow for protecting FPGA-based systems against single event upsets

Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

Volumn , Issue , 2005, Pages 436-444

  Sterpone, L ^a   Violante, M ^a  

^a POLITECNICO DI TORINO   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

BENCHMARKING; COMPUTER AIDED SOFTWARE ENGINEERING; DESIGN; INTEGRATED CIRCUITS; STATIC RANDOM ACCESS STORAGE;

AD-HOC DEVELOPED TOOLS; BENCHMARK CIRCUITS; SINGLE-EVENT UPSETS;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 28444473804     PISSN: 15505774     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (14)

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