Synthesis of low-cost parity-based partially self-checking circuits

Proceedings - 9th IEEE International On-Line Testing Symposium, IOLTS 2003

Volumn , Issue , 2003, Pages 35-40

  Mohanram, K ^a   Sogomonyan, E S ^b   Gossel M ^b   Touba, N A ^a  

^a The University of Texas at Austin   (United States)

^b UNIVERSITY OF POTSDAM   (Germany)

Author keywords

Circuit faults; Circuit noise; Circuit synthesis; Circuit testing; Concurrent computing; Crosstalk; Electrical fault detection; Error analysis; Fault detection; Logic circuits

Indexed keywords

COMPUTATION THEORY; COSTS; CROSSTALK; ELECTRIC FAULT LOCATION; ELECTRIC NETWORK ANALYSIS; ERROR ANALYSIS; ERROR DETECTION; ERRORS; FAULT DETECTION; SYNTHESIS (CHEMICAL);

CIRCUIT FAULTS; CIRCUIT NOISE; CIRCUIT SYNTHESIS; CIRCUIT TESTING; CONCURRENT COMPUTING; ELECTRICAL FAULT DETECTIONS;

LOGIC CIRCUITS;

EID: 3142747413     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/OLT.2003.1214364     Document Type: Conference Paper

References (13)

1. M. Boudjit, et al., "Automatic Generation Algorithms, Experiments and Comparisons of Self-Checking PLA Schemes using Parity Codes," Proc. European Conf. on Design Automation, pp. 144-150, Feb. 1993.
2. C. L. Chen and M. Y. Hsiao, "Error-Correcting Codes for Semiconductor Memory Applications: A State-of-the-Art Review," IBM Journal of Research and Development, Vol. 28, No. 2, pp. 124-134, Mar. 1984.
3. S. Gorshe and B. Bose, "A Self-Checking ALU Design with Efficient Codes," Proc. IEEE Intl. VLSI Test Sym., pp. 157-161, 1996.
4. G. D. Hachtel and F. Somenzi, Logic Synthesis and Verification Algorithms, Kluwer Academic Pub., 1998.
5. P. Lidén, et al., "On Latching Probability of Particle-Induced Transients in Combinational Networks" Proc. Intl. Sym. on Fault-Tolerant Computing, pp. 340-349, 1994.
6. S. Mitra and E. J. McCluskey, "Which Concurrent Error Detection Scheme To Choose?," Proc. IEEE Intl. Test Conf., pp. 985-994, 2000.
7. D. K. Pradhan, Fault Tolerant Computing - Theory and Techniques, Vol. 1, Prentice-Hall, 1986.
8. E. M. Sentovich, et al., "SIS: A System for Sequential Circuit Synthesis," TRM No. UCB/ERL M92/41, Univ. of California, Berkeley, 1992.
9. P. Shivakumar, et al., "Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic," Proc. Intl. Conf. on Dependable Systems and Networks, pp. 389-398, 2002.
10. J. E. Smith and G. Metze, "Strongly Fault Secure Logic Networks," IEEE Trans. on Computers, Vol. C-27, pp. 491-499, Jun. 1978.
11. J. B. Sulistyo and D. S. Ha, "Developing Standard Cells for TSMC 0.25μ Technology under MOSIS DEEP Rules", Department of Electrical and Computer Engineering, Virginia Tech, TR VISC-2002-01, Jan. 2002.
12. J. F. Wakerly, Error Detecting Codes, Self-Checking Circuits and Applications, North-Holland, 1978.
13. S. Yang, "Logic Synthesis and Optimization Benchmarks User Guide," TR 1991-IWLS-UG-Saeyang, MCNC, Research Triangle Park, NC, Jan. 1991.