Off-line testing of delay faults in NoC interconnects

Proceedings of the 9th EUROMICRO Conference on Digital System Design: Architectures, Methods and Tools, DSD 2006

Volumn , Issue , 2006, Pages 677-680

  Bengtsson, Tomas ^a   Jutman, Artur ^b   Kumar, Shashi ^a   Ubar, Raimund ^b   Zebo, Peng ^c  

^a JÖNKÖPING UNIVERSITY   (Sweden)

^b TALLINN UNIVERSITY OF TECHNOLOGY   (Estonia)

^c LINKÖPING UNIVERSITY   (Sweden)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER HARDWARE; ELECTRIC CLOCKS; ELECTRIC FAULT CURRENTS; ONLINE SYSTEMS;

ANALYTICAL ANALYSIS; DELAY FAULTS; HIGH CLOCK SPEEDS; SUB-MICRON CHIPS;

MICROPROCESSOR CHIPS;

EID: 34547975744     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DSD.2006.72     Document Type: Conference Paper

References (13)

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