All digital built-in delay and crosstalk measurement for on-chip buses

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2000, Pages 527-531

  Su, Chauchin ^a   Chen, Yue Tsang ^a   Huang, Mu Jeng ^a   Chen, Gen Nan ^a   Lee, Chung Len ^b  

^a NATIONAL CENTRAL UNIVERSITY   (Taiwan)

^b NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ALL DIGITAL; DELAY FAULTS; DIAGNOSIS PROCEDURE; HARDWARE OVERHEADS; MEASUREMENT METHODOLOGY; ON-CHIP BUS; SPICE SIMULATIONS;

DESIGN; EXHIBITIONS;

CROSSTALK;

EID: 33744458086     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2000.840836     Document Type: Conference Paper

References (8)

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3. P.J. Restle, et. al., "Measurement and Modeling of On-Chip Transmission Line Effects in a 400 MHz Microprocessor," IEEE J. of Solid State Circuits, April 1998, pp.882-885.
4. D.H. Cho, et. al., "Interconnect Capacitance, Crosstalk, and Signal Delay for 0.35m CMOS Technology, Proc. IEDM 1996, pp.619-622.
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7. W. Chen, S.K. Gupta, and M.A. Breuer, "Analytic Models for Crosstalk Delay and Pulse Analysis Under Non-Ideal Inputs," Proc. IEEE Int'l Test Conference, 1997, pp.809-818.
8. L. Schnell, Technology of Electrical Measurements, Jone Wiley & Sons Ltd., New York, U.S.A., 1993.