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Volumn , Issue , 2004, Pages 2-7

At-speed on-chip diagnosis of board-level interconnect faults

Author keywords

[No Author keywords available]

Indexed keywords

BOARD-LEVEL INTERCONNECT FAULTS; FAULT TESTING; INTERCONNECT FAULTS; LINEAR FEEDBACK SHIFT REGISTER (LFSR); MULTIPLE INPUT SHIFT REGISTER (MISR);

EID: 15844403475     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ETSYM.2004.1347572     Document Type: Conference Paper
Times cited : (40)

References (15)
  • 2
    • 0037341498 scopus 로고    scopus 로고
    • Minimizing pattern count for interconnect test under a ground bounce constraint
    • March-April
    • E.J. Marinissen, B. Vermeulen, H. Hollmann, R.G. Bennetts, "Minimizing Pattern Count for Interconnect Test under a Ground Bounce Constraint," in IEEE D&T of Comp., March-April 2003, pp. 8-18.
    • (2003) IEEE D&T of Comp. , pp. 8-18
    • Marinissen, E.J.1    Vermeulen, B.2    Hollmann, H.3    Bennetts, R.G.4
  • 3
    • 0035441029 scopus 로고    scopus 로고
    • Switching activity generation with automated BIST synthesis for performance testing of interconnects
    • R.Pendurkar,A.Chatterjee,Y.Zorian,"Switching Activity Generation with Automated BIST Synthesis for Performance Testing of Interconnects," IEEE Trans CAD/ICS, vol.20, no.9, 2001.
    • (2001) IEEE Trans CAD/ICS , vol.20 , Issue.9
    • Pendurkar, R.1    Chatterjee, A.2    Zorian, Y.3
  • 4
    • 0033309294 scopus 로고    scopus 로고
    • An embedded technique for at-speed interconnect testing
    • B.Nadeau-Dostie,et.al,"An Embedded Technique for At-Speed Interconnect Testing," in Proc.ITC'99, pp.431-438.
    • Proc.ITC'99 , pp. 431-438
    • Nadeau-Dostie, B.1
  • 5
    • 0035683903 scopus 로고    scopus 로고
    • Testing interconnects for noise and skew in gigahertz SoC
    • A.Attarha,M.Nourani,"Testing Interconnects for Noise and Skew in Gigahertz SoC," in Proc of ITC'2001, pp.305-314.
    • Proc of ITC'2001 , pp. 305-314
    • Attarha, A.1    Nourani, M.2
  • 6
    • 3142743071 scopus 로고    scopus 로고
    • A new IEEE 1149.1 boundary scan design for the detection of delay defects
    • S.Park, T.Kim, "A new IEEE 1149.1 boundary scan design for the detection of delay defects," in Proc. DATE'2000, pp. 458-462.
    • Proc. DATE'2000 , pp. 458-462
    • Park, S.1    Kim, T.2
  • 8
    • 0015960393 scopus 로고
    • Testing of faults in wiring interconnects
    • W.H. Kautz, "Testing of Faults in Wiring Interconnects," IEEE Trans. Computers, vol. 23, no. 4, 1974, pp. 358-363.
    • (1974) IEEE Trans. Computers , vol.23 , Issue.4 , pp. 358-363
    • Kautz, W.H.1
  • 9
    • 0020307902 scopus 로고
    • Electronic chip-in-place test
    • IEEE Press
    • P. Goel and M.T. McMahon, "Electronic Chip-in-Place Test," Proc. ITC 82, IEEE Press, 1982, pp. 83-90.
    • (1982) Proc. ITC 82 , pp. 83-90
    • Goel, P.1    McMahon, M.T.2
  • 12
    • 0032314041 scopus 로고    scopus 로고
    • Boundary scan BIST methodology for reconfigurable systems
    • C.Su, S.W.Jeng, Y.T.Chen, "Boundary scan BIST methodology for reconfigurable systems," in Proc. ITC'98, IEEE Press, 1998, pp. 774-783.
    • (1998) Proc. ITC'98, IEEE Press , pp. 774-783
    • Su, C.1    Jeng, S.W.2    Chen, Y.T.3
  • 14
    • 0035687725 scopus 로고    scopus 로고
    • Configuration free SoC interconnect BIST methodology
    • C.Su,W.Tseng,"Configuration Free SoC Interconnect BIST Methodology," in Proc. ITC'2001, pp.1033-1038.
    • Proc. ITC'2001 , pp. 1033-1038
    • Su, C.1    Tseng, W.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.