Design and implementation of a pipelined bit-serial SFQ microprocessor, CORE1β

IEEE Transactions on Applied Superconductivity

Volumn 17, Issue 2, 2007, Pages 474-477

  Yamanashi, Y ^a   Tanaka, M ^b   Akimoto, A ^a   Park, H ^a   Kamiya, Y ^b   Irie, N ^b   Yoshikawa, N ^a   Fujimaki, A ^b   Terai, H ^c   Hashimoto, Y ^d  

^a YOKOHAMA NATIONAL UNIVERSITY   (Japan)

^b NAGOYA UNIVERSITY   (Japan)

^c NATIONAL INSTITUTE OF INFORMATION AND COMMUNICATIONS TECHNOLOGY   (Japan)

^d SUPERCONDUCTIVITY RESEARCH LABORATORY   (Japan)

Author keywords

Josephson logic; Microprocessors; Pipelining; SFQ circuits; Superconducting integrated circuits

Indexed keywords

ELECTRIC POWER UTILIZATION; JOSEPHSON JUNCTION DEVICES; LOGIC CIRCUITS; QUANTUM THEORY;

JOSEPHSON LOGIC; PIPELINING; SFQ CIRCUITS; SUPERCONDUCTING INTEGRATED CIRCUITS;

MICROPROCESSOR CHIPS;

EID: 34547504707     PISSN: 10518223     EISSN: None     Source Type: Journal    
DOI: 10.1109/TASC.2007.898606     Document Type: Conference Paper

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