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Volumn 16, Issue 12, 2003, Pages 1456-1459

Design and high-speed test of (4 × 8)-bit single-flux-quantum shift register files

Author keywords

[No Author keywords available]

Indexed keywords

FLIP FLOP CIRCUITS; JOSEPHSON JUNCTION DEVICES; LOGIC DESIGN; RANDOM ACCESS STORAGE; SHIFT REGISTERS;

EID: 0346343006     PISSN: 09532048     EISSN: None     Source Type: Journal    
DOI: 10.1088/0953-2048/16/12/030     Document Type: Conference Paper
Times cited : (12)

References (11)
  • 1
    • 0026116572 scopus 로고
    • RSFQ logic/memory family: A new Josephson-junction technology for sub-terahertz-clock frequency digital systems
    • Likharev K K and Semenov V K 1991 RSFQ logic/memory family: a new Josephson-junction technology for sub-terahertz-clock frequency digital systems IEEE Trans. Appl. Supercond. 1 3
    • (1991) IEEE Trans. Appl. Supercond. , vol.1 , pp. 3
    • Likharev, K.K.1    Semenov, V.K.2
  • 2
    • 0035268645 scopus 로고    scopus 로고
    • FLUX chip: Design of a 20-GHz 16-bit ultrapipelined RSFQ processor prototype based on 1.75-μm LTS technology
    • Dorojevets M, Bunyk P and Zinoviev D 2001 FLUX chip: design of a 20-GHz 16-bit ultrapipelined RSFQ processor prototype based on 1.75-μm LTS technology IEEE Trans. Appl. Supercond. 11 326
    • (2001) IEEE Trans. Appl. Supercond. , vol.11 , pp. 326
    • Dorojevets, M.1    Bunyk, P.2    Zinoviev, D.3
  • 3
    • 0036505091 scopus 로고    scopus 로고
    • High-end server based on complexity-reduced architecture for superconductor technology
    • Fujimaki A, Takai Y and Yoshikawa N 2002 High-end server based on complexity-reduced architecture for superconductor technology IEICE Trans. Electron. 85 612
    • (2002) IEICE Trans. Electron. , vol.85 , pp. 612
    • Fujimaki, A.1    Takai, Y.2    Yoshikawa, N.3
  • 8
    • 0042756586 scopus 로고
    • Design and testing of rapid single flux quantum shift registers with magnetically coupled readout gates
    • Yup P and Mukhanov O A 1992 Design and testing of rapid single flux quantum shift registers with magnetically coupled readout gates IEEE Trans. Appl. Supercond. 2 214
    • (1992) IEEE Trans. Appl. Supercond. , vol.2 , pp. 214
    • Yup, P.1    Mukhanov, O.A.2
  • 10
    • 0012306549 scopus 로고    scopus 로고
    • Design and component test of RSFQ packet decoders for shift register memories
    • Fujiwara K, Hoshina H, Koshiyama J and Yoshikawa N 2002 Design and component test of RSFQ packet decoders for shift register memories Physica C 378 1475
    • (2002) Physica C , vol.378 , pp. 1475
    • Fujiwara, K.1    Hoshina, H.2    Koshiyama, J.3    Yoshikawa, N.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.