Demonstration of a single-flux-quantum microprocessor using passive transmission lines

IEEE Transactions on Applied Superconductivity

Volumn 15, Issue 2 PART I, 2005, Pages 400-404

  Tanaka, M ^a   Kondo, T ^a   Nakajima, N ^b   Kawamoto, T ^a   Yamanashi, Y ^b   Kamiya, Y ^a   Akimoto, A ^b   Fujimaki, A ^a   Hayakawa, H ^a   Yoshikawa, N ^b   Terai, H ^c   Hashimoto, Y ^d   Yorozu, S ^d  

^a NAGOYA UNIVERSITY   (Japan)

^b YOKOHAMA NATIONAL UNIVERSITY   (Japan)

^c NATIONAL INSTITUTE OF INFORMATION AND COMMUNICATIONS TECHNOLOGY   (Japan)

^d SUPERCONDUCTIVITY RESEARCH LABORATORY   (Japan)

Author keywords

Microprocessor; Passive transmission line; Single flux quantum (SFQ) logic

Indexed keywords

DATA STORAGE EQUIPMENT; DATA TRANSFER; ELECTRIC CURRENTS; ELECTRIC LINES; ELECTRIC POTENTIAL; JOSEPHSON JUNCTION DEVICES; LSI CIRCUITS; SERVERS; SUPERCONDUCTIVITY;

LSI TECHNOLOGY; MILLION INSTRUCTION PER SECOND (MIPS); PASSIVE TRANSMISSION LINES (PTL); SINGLE FLUX QUANTUM (SFQ) LOGIC;

MICROPROCESSOR CHIPS;

EID: 22144454607     PISSN: 10518223     EISSN: None     Source Type: Journal    
DOI: 10.1109/TASC.2005.849860     Document Type: Conference Paper

References (14)

1. K. K. Likharev and V. K. Semenov, "RSFQ logic/memory family: A new Josephson-junction digital technology for sub-terahertz-clock-frequency digital systems," IEEE Trans. Appl. Supercond., vol. 1, pp. 3-28, Mar. 1991.
2. M. Dorojevets, P. Bunyk, and D. Zinoviev, "FLUX chip: Design of a 20-GHz 16-bit ultrapipelined RSFQ processor prototype based on 1.75-μm LTS technology," IEEE Trans. Appl. Supercond., vol. 11, pp. 326-332, Mar. 2001.
3. A. Fujimaki, Y. Takai, and N. Yoshikawa, "High-end server based on complexity-reduced architecture for superconductor technology," IEICE Trans. Electron., vol. E85-C, pp. 612-616, Mar. 2002.
4. M. Tanaka, F. Matsuzaki, T. Kondo, N. Nakajima, Y. Yamanashi, H. Terai, S. Yorozu, N. Yoshikawa, A. Fujimaki, and H. Hayakawa, "Prototypic design of the single-flux-quantum microprocessor, CORE1," Supercond. Sci. Technol., vol. 16, no. 12, pp. 1460-1463, Dec. 2003.
5. M. Tanaka, F. Matsuzaki, T. Kondo, N. Nakajima, Y. Yamanashi, A. Fujimaki, H. Hayakawa, N. Yoshikawa, H. Terai, and S. Yorozu, "A single-flux-quantum logic prototype microprocessor," in Tech. Dig. IEEE Int. Solid-State Circuits Conf., San Francisco, CA, Feb. 2004.
6. K. Fujiwara, Y. Yamashiro, N. Yoshikawa, A. Fujimaki, H. Terai, and S. Yorozu, "Design and high-speed test of (4 × 8)-bit single-flux-quantum shift register files," Supercond. Sci. Technol., vol. 16, no. 12, pp. 1456-1459, Dec. 2003.
7. Y. Hashimoto, S. Yorozu, Y. Kameda, and V. K. Semenov, "A design approach to passive interconnects for single flux quantum logic cells," IEEE Trans. Appl. Supercond., vol. 13, no. 2, pp. 535-538, Jun. 2003.
8. Y. Hashimoto, S. Yorozu, Y. Kameda, A. Fujimaki, H. Terai, and N. Yoshikawa, "Demonstration of passive interconnection between single-flux-quantum circuit blocks," in Extended Abstracts 9th Int. Supercond. Electron. Conf., Sydney, Australia, Jul. 2003.
9. M. Ito, N. Nakajima, K. Fujiwara, N. Yoshikawa, A. Fujimaki, H. Terai, and S. Yorozu, "Design and implementation of SFQ programmable clock generators," Physica C, pt. 2, vol. 412-414, pp. 1550-1554, to be published.
10. M. Tanaka, T. Kondo, A. Sekiya, A. Fujimaki, H. Hayakawa, F. Matsuzaki, N. Yoshikawa, H. Terai, and S. Yorozu, "Component test toward single-flux-quantum processors," Physica C, pt. 2, vol. 392-396, pp. 1490-1494, Oct. 2003.
11. S. Yorozu, Y. Kameda, H. Terai, A. Fujimaki, T. Yamada, and S. Tahara, "A single flux quantum standard logic cell library," Physica C, pt. 2, vol. 378-381, pp. 1471-1474, Oct. 2002.
12. N. Yoshikawa, T. Nishigai, H. Kojima, K. Fujiwara, A. Fujimaki, T. Yamada, M. Tanaka, S. Yorozu, M. Hidaka, and H. Terai, "Magnetic shielding against DC bias current toward large-scale SFQ integrated circuits," in Appl. Supercond. Conf., Jacksonville, FL, Oct. 2004.
13. S. Nagasawa, Y. Hashimoto, H. Numata, and S. Tahara, "A 380 ps, 9.5 mW Josephson 4-Kbit RAM operated at a high bit," IEEE Trans. Appl. Supercond., vol. 5, pp. 2447-2452, Jun. 1995.
14. E. S. Fang and T. V. Duzer, "A Josephson Integrated Circuit Simulator (JSIM) for superconductive electronics application," in Extended Abstracts Int. Supercond. Electron. Conf., Tokyo, Japan, Jun. 1989.