Reconfigurable acceleration for Monte Carlo based financial simulation

Proceedings - 2005 IEEE International Conference on Field Programmable Technology

Volumn 2005, Issue , 2005, Pages 215-222

  Zhang, G L ^a   Leong, P H W ^a   Ho, C H ^a   Tsoi, K H ^a   Lee, Dong U ^b   Cheung, C C C ^c   Cheung, R C C ^d   Luk, W ^d  

^a CHINESE UNIVERSITY OF HONG KONG   (Hong Kong)

^b UNIVERSITY OF CALIFORNIA   (United States)

^c Cluster Technology Ltd   (Hong Kong)

^d IMPERIAL COLLEGE LONDON   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

GAUSSIAN DISTRIBUTED RANDOM NUMBERS; GENERIC ARCHITECTURE; HARDWARE ACCELERATORS; PRICING DERIVATIVES; FINANCIAL APPLICATIONS; FINANCIAL SIMULATIONS; IN-FIELD; INSTRUCTION PROCESSORS; MONTE CARLO'S SIMULATION; NOVEL HARDWARE; ON CHIPS; RECONFIGURABLE;

COMPUTER ARCHITECTURE; COMPUTER SIMULATION; FINANCIAL DATA PROCESSING; MATHEMATICAL MODELS; MONTE CARLO METHODS; PROGRAM PROCESSORS; APPLICATION PROGRAMS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); FINANCE; NUMBERING SYSTEMS; RANDOM NUMBER GENERATION;

FIELD PROGRAMMABLE GATE ARRAYS; MONTE CARLO METHODS;

EID: 33846585053     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPT.2005.1568549     Document Type: Conference Paper

References (25)

1. T. Todman et al, "Reconfigurable computing: architectures and design methods", IEE Proc.-Computing and Digital Techniques, Vol. 152, No. 2, March 2005, pp. 193-207.
2. J. Vuillemin, B. Patrice, R. Didier, M. Shand, T. Herve and B. Philippe, "Programmable Active Memories: reconfigurable systems corne of age", IEEE Transactions on VLSI Systems, Volume 7, No. 2, pp. 56-59, 1996.
3. J.M. McCollum, J.M. Lancaster, D.W. Bouldin and G.D. Peterson, "Hardware acceleration of pseudo-random number generation for simulation applications," Proceedings of the 35th Annual Southeastern Symposium on System Theory, pp. 299-303, March, 2003.
4. M. Gokhale et al., "Monte Carlo radiative heat transfer simulation", Proc. Field-Prog. Logic and Applications, LNCS 3203, Springer, pp. 95-104, 2004.
5. M. Yoshimi et al., "Stochastic simulation for biochemical reactions on FPGA", Proc. Field-Prog. Logic and Applications, LNCS 3203, Springer, pp. 105-114, 2004.
6. C.P. Cowen and S. Monaghan, "A reconfigurable Monte-Carlo clustering processor (MCCP)", Proc. Field-Programmable Custom Computing Machines (FCCM), pp. 59-65, 1994.
7. A. Postula, D. Abramson and P. Logothetis, "The design of a specialised processor for the Simulation of sintering", Proc. of the 22nd EUROMICRO Conference, pp. 501-508, 1996.
8. K.H. Tsoi, C.H. Ho, H.C. Yeung and P.H.W. Leong, "An arithmetic library and its application to the N-body problem," Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), 2004.
9. A. Brace, D. Ga̧tarek and M. Musiela, "The market model of interest rate dynamics," Mathematical Finance, Volume 7, No. 2, pp. 127-155, April, 1997.
10. G.E.P. Box et al., "A note on the generation of random normal deviates," Ann. Math. Statist., Vol. 29, pp. 610-611, 1958.
11. R. Pietersz, A. Pelsser and M. van Regenmortel, "Fast drift approximated pricing in the BGM model," November, 2002.
12. J.C. Hull, Option, futures, and other derivatives, 4th ed. Prentice Hall, Upper Saddle River, 2000.
13. D.E. Knuth, "Seminumerical algorithms", The Art of Computer Programming, Vol. 2, Addison-Wesley, 1997.
14. Xilinx Inc., "Using the Virtex Block SelectRAM+ features," Application Note: Virtex Series, XAPP130, Dec. 2000.
15. J. Nelder and R. Mead, "A simplex method for function minimization," Computer Journal, Vol. 7, pp. 308-313, 1965.
16. P. Hung, H. Fahmy, O. Mencer, M.J. Flynn, "Fast division algorithm with a small lookup table," Conference Record of the Thirty-Third Asilomar Conference on Signals, Systems and computers, Vol. 2, pp. 1465-1468, May 1999.
17. J.C. Jeong et al, "A new pipelined divider with a small lookup table," Proc. IEEE Asia-Pacific Conference on ASIC, pp. 33-36, August 2002.
18. I.E. Volder, "The CORDIC trigonometric computing technique", IEEE Trans. on Elec. Comput., vol. EC-8, no. 3, pp. 330-334, 1959.
19. D. Lee et al., "A hardware Gaussian noise generator for channel code evaluation", Proc. IEEE Symp. on Field-Prog. Cust. Comput. Mach., pp. 69-78, 2003.
20. D. Lee, W. Luk, J. Villasenor and P.Y.K. Cheung, "Hardware function evaluation using non-linear segments", Proc. Field-Prog. Logic and Applications, LNCS 2778, Springer-Verlag, pp. 796-807, 2003.
21. C. Jones, E. Vallés, M. Smith and J. Villasenor, "Approximate-min* constraint node updating for LDPC code decoding", Proc. IEEE Military Comm. Conf., 2003.
22. International Business Machines Corporation, "The CoreConnect bus architecture," http://www.chips.ibm.com/products/coreconnect, 1999.
23. Xilinx Inc., "Adding user cores to your embedded system," User Core Templates Reference Guide, January 2004.
24. Xilinx Inc., "ML310 Development Platform," URL http://www.xilinx.com/univ/ML310/ml310_mainpage.html, 2004.
25. N. Shirazi, W. Luk and P.Y.K. Cheung, "Framework and tools for run-time reconfigurable designs", IEE Proc. Comput. Digit. Tech., pp. 147-152, May 2000.