IBM powerPC 440 FPU with complex-arithmetic extensions

IBM Journal of Research and Development

Volumn 49, Issue 2-3, 2005, Pages 249-254

  Wait, Charles D ^a  

^a IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; DATA STORAGE EQUIPMENT; DIGITAL ARITHMETIC; EMBEDDED SYSTEMS; INTERFACES (COMPUTER); MICROPROCESSOR CHIPS; PARALLEL PROCESSING SYSTEMS; SHIFT REGISTERS;

AUXILIARY PROCESSOR UNIT (APU) INTERFACE; FLOATING POINT INSTRUCTION SET; FLOATING POINT UNIT; SINGLE INSTRUCTION MULTIPLE DATA; STORAGE BUSES;

PERSONAL COMPUTERS;

EID: 19344362622     PISSN: 00188646     EISSN: None     Source Type: Journal    
DOI: 10.1147/rd.492.0249     Document Type: Article

References (5)

1. K. Dockser, "'Honey, I Shrunk the Supercomputer,' - The PowerPC 440 FPU Brings Supercomputing to IBM's Blue Logic Library," IBM MicroNews 7, No. 4, 27-29 (Fourth Quarter 2001); see http://www-306.ibm.com/chips/micronews/vol7_no4/mn_vol7_no4_fnl. pdf.
2. IBM Corporation, PPC440×5 CPU Core User's Manual, Publication No. SA14-2613-03, June 2001; see http://www-306.ibm.com/chips/techlib/ techlib.nsf/products/PowerPC_440_Embedded_Core.
3. IBM Corporation, Book E: Enhanced PowerPC Architecture, March 2000.
4. IEEE Standard 754, "IEEE Standard for Binary Floating-Point Arithmetic," © 1985 IEEE.
5. S. Chatterjee, L. R. Bachega, P. Bergner, K. A. Dockser, J. A. Gunnels, M. Gupta, F. G. Gustavson, C. A. Lapkowski, G. K. Liu, M. Mendell, R. Nair, C. D. Wait, T. J. C. Ward, and P. Wu, "Design and Exploitation of a High-Performance SIMD Floating-Point Unit for Blue Gene/L," IBM J. Res. & Dev. 49, No. 2/3, 377-391 (2005, this issue).