Blue Gene/L compute chip: Synthesis, timing, and physical design

IBM Journal of Research and Development

Volumn 49, Issue 2-3, 2005, Pages 277-287

  Bright, Arthur A ^a   Haring, Ruud A ^a   Dombrowa, Marc B ^a   Ohmacht, Martin ^a   Hoenicke, Dirk ^a   Singh, Sarabjeet ^a   Marcella, James A ^b   Lembach, Robert F ^b   Douskey, Steven M ^b   Ellavsky, Matthew R ^b   Zoellin, Christian G ^c   Gara, Alan ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b IBM   (United States)

^c IBM   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER CIRCUITS; CAPACITORS; CMOS INTEGRATED CIRCUITS; COMPUTER HARDWARE DESCRIPTION LANGUAGES; DYNAMIC RANDOM ACCESS STORAGE; PARALLEL PROCESSING SYSTEMS; STATIC RANDOM ACCESS STORAGE; SUPERCOMPUTERS;

BUFFERING; CHIP DESIGN; CLOCK TREE; SYSTEM-ON-A-CHIP;

APPLICATION SPECIFIC INTEGRATED CIRCUITS;

EID: 21044442811     PISSN: 00188646     EISSN: None     Source Type: Journal    
DOI: 10.1147/rd.492.0277     Document Type: Article

References (14)

1. See http://www-3.ibm.com/chips/products/powerpc/cores/.
2. C. D. Wait, "The PowerPC 440 FPU with Complex-Arithmetic Extensions," IBM J. Res. & Dev. 49, No. 2/3, 249-254 (2005, this issue).
3. R. A. Haring, R. Bellofatto, A. A. Bright, P. G. Crumley, M. B. Dombrowa, S. M. Douskey, M. R. Ellavsky, B. Gopalsamy, D. Hoenicke, T. A. Liebsch, J. A. Marcella, and M. Ohmacht, "Blue Gene/L Compute Chip: Control, Test, and Bring-Up Infrastructure," IBM J. Res. & Dev. 49, No. 2/3, 28-301 (2005, this issue).
4. J. E. Barth, Jr., J. H. Dreibelbis, E. A. Nelson, D. L. Anand, G. Pomichter, P. Jakobsen, M. R. Nelms, J. Leach, and G. M. Belansek, "Embedded DRAM Design and Architecture for the IBM 0.11-μm ASIC Offering," IBM J. Res. & Dev. 46, No. 6, 675-689 (2002).
5. S. S. Iyer, J. E. Barth, Jr., P. C. Parries, J. P. Norum, J. P. Rice, L. R. Logan, and D. Hoyniak, "Embedded DRAM: Technology Platform for the Blue Gene/L Chip," IBM J. Res. & Dev. 49, No. 2/3, 333-350 (2005, this issue).
6. See http://www-3.ibm.com/chips/products/asics/products/cu-11.html.
7. N. R. Adiga, M. A. Blumrich, D. Chen, P. Coteus, A. Gara, M. E. Giampapa, P. Heidelberger, S. Singh, B. D. Steinmacher-Burow, T. Takken, M. Tsao, and P. Vranas, "Blue Gene/L Torus Interconnection Network," IBM J. Res. & Dev. 49, No. 2/3, 265-276 (2005, this issue).
8. See http://www-3.ibm.com/chips/products/asics/methodology/.
9. L. Trevillyan, D. Kung, R. Puri, L. N. Reddy, and M. A. Kazda, "An Integrated Environment for Technology Closure of Deep-Submicron IC Designs," IEEE Design & Test Computers 21, No. 1, 14-22 (2004).
10. A. Kuehlmann, A. Srinivasan, and D. P. LaPotin, "Verity - A Formal Verification Program for Custom CMOS Circuits," IBM J. Res. & Dev. 39, No. 1/2, 149-165 (1995).
11. J. Schutz and C. Webb, "A Scalable X86 CPU Design for 90nm Process," IEEE International Solid-State Circuits Conference, Digest of Technical Papers, 2004, pp. 62-71.
12. P. Coteus, H. R. Bickford, T. M. Cipolla, P. G. Crumley, A. Gara, S. A. Hall, G. V. Kopcsay, A. P. Lanzetta, L. S. Mok, R. Rand, R. Swetz, T. Takken, P. La Rocca, C. Marroquin, P. R. Germann, and M. J. Jeanson, "Packaging the Blue Gene/L Supercomputer," IBM J. Res. & Dev. 49, No. 2/3, 213-548 (2005, this issue).
13. P. J. Restle, T. G. McNamara, D. A. Webber, P. J. Camporese, K. F. Eng, K. A. Jenkins, D. H. Allen, M. J. Rohn, M. P. Quaranta, D. W. Boerstler, C. J. Alpert, C. A. Carter, R. N. Bailey, J. G. Petrovick, B. L. Krauter, and B. D. McCredie, "A Clock Distribution Network for Microprocessors," IEEE J. Solid-State Circuits 36, No. 5, 792-799 (2001).
14. M. Ohmacht, R. A. Bergamaschi, S. Bhattacharya, A. Gara, M. E. Giampapa, B. Gopalsamy, R. A. Haring, D. Hoenicke, D. J. Krolak, J. A. Marcella, B. J. Nathanson, V. Salapura, and M. E. Wazlowski, "Blue Gene/L Compute Chip: Memory and Ethernet Subsystem," IBM J. Res. & Dev. 49, No. 2/3, 255-264 (2005, this issue).