Configurable, high throughput, irregular LDPC decoder architecture: Tradeoff analysis and implementation

Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors

Volumn , Issue , 2006, Pages 360-367

  Karkooti, Marjan ^a   Radosavljevic, Predrag ^a   Cavallaro, Joseph R ^a  

^a Rice University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CODE LENGTHS; CODE RATES; LOW DENSITY PARITY CHECK (LDPC); TRADEOFF ANALYSIS;

CODES (SYMBOLS); DATA REDUCTION; ERROR CORRECTION; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); SOFTWARE PROTOTYPING; WIRELESS NETWORKS;

COMPUTER ARCHITECTURE;

EID: 34547398974     PISSN: 10636862     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASAP.2006.23     Document Type: Conference Paper

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