Performance optimization of synchronous control units for datapaths with variable delay arithmetic units

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn 2003-January, Issue , 2003, Pages 816-819

  Kim, Euiseok ^a,b   Lee, Dong Ik ^b   Saito, H ^a   Nakamura, H ^a   Lee, Jeong Gun ^b   Nanya, T ^a  

^a UNIVERSITY OF TOKYO   (Japan)

^b Gwangju Institute of Science and Technology (GIST)   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; DESIGN;

ARITHMETIC UNIT; DATA-PATHS; OPTIMIZATION METHOD; OPTIMIZATION TECHNIQUES; PERFORMANCE OPTIMIZATIONS; SYNCHRONOUS CONTROL; TARGET SYSTEMS; VARIABLE DELAYS;

PROGRAM PROCESSORS;

EID: 34547349028     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2003.1195130     Document Type: Conference Paper

References (7)

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7. S. Narayan and D. D. Gajski, "System Clock Estimation Based on Clock Slack Minimization," In Proceedings of DAC'92, pp.66-71, Sep. 1992.