Design hierarchy-guided multilevel circuit partitioning

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 22, Issue 4, 2003, Pages 420-427

  Cheon, Yongseok ^a   Wong, Martin D F ^b  

^a University of Texas at Austin   (United States)

^b University of Illinois at Urbana Champaign   (United States)

Author keywords

Clustering; Design hierarchy; Multilevel partitioning; Rent's rule

Indexed keywords

ALGORITHMS; FIELD PROGRAMMABLE GATE ARRAYS; INTEGRATED CIRCUIT LAYOUT; NUMERICAL METHODS; OPTIMIZATION; TREES (MATHEMATICS);

FLAT NETLIST HYPERGRAPH; MULTILEVEL CIRCUIT PARTITIONING;

VLSI CIRCUITS;

EID: 0037390559     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2003.809659     Document Type: Article

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