-
2
-
-
84858093070
-
-
Physical Design Modelling and Verification Project SPACE Project
-
Physical Design Modelling and Verification Project (SPACE Project). http://cas.et.tudelft.nl/research/space/html.
-
-
-
-
3
-
-
0022769976
-
Graph based algorithms for Boolean function representation
-
August
-
R. E. Bryant. Graph based algorithms for Boolean function representation. IEEE Transactions on Computers, C-35:677-690, August 1986.
-
(1986)
IEEE Transactions on Computers
, vol.C-35
, pp. 677-690
-
-
Bryant, R.E.1
-
4
-
-
3042567212
-
Exploiting crosstalk to speed up on-chip buses
-
Paris, France, Feb
-
C. Duan and S. Khatri. Exploiting crosstalk to speed up on-chip buses. In Proceedings, Design, Automation and Test in Europe Conference and Exhibition, volume 2, pages 778-783, Paris, France, Feb 2004.
-
(2004)
Proceedings, Design, Automation and Test in Europe Conference and Exhibition
, vol.2
, pp. 778-783
-
-
Duan, C.1
Khatri, S.2
-
5
-
-
84950134284
-
Analysis and avoidance of cross-talk lit on-chip buses
-
Stanford, CA, Aug
-
C. Duan, A. Tirumala, and S. Khatri. Analysis and avoidance of cross-talk lit on-chip buses. In Hot Interconnects 9, pages 133-138, Stanford, CA, Aug 2001.
-
(2001)
Hot Interconnects 9
, pp. 133-138
-
-
Duan, C.1
Tirumala, A.2
Khatri, S.3
-
7
-
-
84893650459
-
A bus delay reduction technique considering crosstalk
-
Paris, Frnnce, Mar
-
K. Hirose and H. Yasuura. A bus delay reduction technique considering crosstalk. In Proceedings of Design, Automation and Test in Europe (DATE), pages 441-445, Paris, Frnnce, Mar 2000.
-
(2000)
Proceedings of Design, Automation and Test in Europe (DATE)
, pp. 441-445
-
-
Hirose, K.1
Yasuura, H.2
-
8
-
-
84858093068
-
-
The International Technology Roadmap for Semiconductors
-
The International Technology Roadmap for Semiconductors, http://public.itrs.net, 2003.
-
(2003)
-
-
-
10
-
-
0032678594
-
A novel VLSI layout fabric for deep sub-micron applications
-
New Orleans, June
-
S. Khatri, A. Mehrotra, R. Brayton, A. Sangiovanni-Vincentelli, and R. Otten. A novel VLSI layout fabric for deep sub-micron applications. In Proceedings of'the Design Automation Conference, New Orleans, June 1999.
-
(1999)
Proceedings of'the Design Automation Conference
-
-
Khatri, S.1
Mehrotra, A.2
Brayton, R.3
Sangiovanni-Vincentelli, A.4
Otten, R.5
-
11
-
-
0031383346
-
A repeater optimization methodology for deep sub-micron, high-performance processors
-
Austin, TX, Oct
-
D. Li, A. Pua, P. Srivastava, and U. Ko. A repeater optimization methodology for deep sub-micron, high-performance processors. In IEEE International Conference on Computer Design: VLSI in Computers and Proceaors (ICCD), pages 726-731, Austin, TX, Oct 1997.
-
(1997)
IEEE International Conference on Computer Design: VLSI in Computers and Proceaors (ICCD)
, pp. 726-731
-
-
Li, D.1
Pua, A.2
Srivastava, P.3
Ko, U.4
-
13
-
-
0038453533
-
Wire placement for crosstalk energy minimization in address buses
-
Paris, France, Mar
-
L. Macchiarulo, E. Macii, and M. Poncino. Wire placement for crosstalk energy minimization in address buses. In Proceedings of Design, Automation and Test in Europe (DATE), pages 158-162, Paris, France, Mar 2002.
-
(2002)
Proceedings of Design, Automation and Test in Europe (DATE)
, pp. 158-162
-
-
Macchiarulo, L.1
Macii, E.2
Poncino, M.3
-
15
-
-
84949766294
-
-
P. Sotiriadis and A. Chandraknsan. Reducing bus delay in submicron technology using coding. In Proceedings Asia and South Pacific Design Automation Conference (ASP-DAC), pages 109-114, Yokohama, Japan, Jan/Fob 2001.
-
P. Sotiriadis and A. Chandraknsan. Reducing bus delay in submicron technology using coding. In Proceedings Asia and South Pacific Design Automation Conference (ASP-DAC), pages 109-114, Yokohama, Japan, Jan/Fob 2001.
-
-
-
-
18
-
-
0031346159
-
Post global routing crosstalk synthesis
-
Dec
-
T. Xue, E. Kuh, and D. Wang. Post global routing crosstalk synthesis. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 16(12):1418-1430, Dec 1997.
-
(1997)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
, vol.16
, Issue.12
, pp. 1418-1430
-
-
Xue, T.1
Kuh, E.2
Wang, D.3
-
19
-
-
0032643013
-
Reducing cross-coupling among interconnect wires in deep-submicron datapath design
-
New Orleans, LA, Jun
-
J.-S. Yim and C.-M. Kyung. Reducing cross-coupling among interconnect wires in deep-submicron datapath design. In Proceedings. 36th Design Automation Conference (DAC), pages 485-490, New Orleans, LA, Jun 1999.
-
(1999)
Proceedings. 36th Design Automation Conference (DAC)
, pp. 485-490
-
-
Yim, J.-S.1
Kyung, C.-M.2
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