-
1
-
-
34447275638
-
-
B. Tavel, T. Skotnicki, G. Pares, N. Carriere, M. Rivoire, F. Leverd, C. Julien, J. Torres, and R. Pantel, Totally silicided (CoSi2) polysilicon: A novel approach to very low-resistivity gate without metal CMP nor etching, in IEDM Tech. Dig., 2001, pp. 37.5.1-37.5.4.
-
B. Tavel, T. Skotnicki, G. Pares, N. Carriere, M. Rivoire, F. Leverd, C. Julien, J. Torres, and R. Pantel, "Totally silicided (CoSi2) polysilicon: A novel approach to very low-resistivity gate without metal CMP nor etching," in IEDM Tech. Dig., 2001, pp. 37.5.1-37.5.4.
-
-
-
-
2
-
-
0842266648
-
-
J. Kedzierski, D. Boyd, P. Ronsheim, S. Zafar, J. Newbury, J. Ott, C. Cabral, Jr., M. Ieong, and W. Haensch, Threshold voltage control in NiSi-gated MOSFETs through silicidation induced impurity segregation (SIIS), in IEDM Tech. Dig., 2003, pp. 13.3.1-13.3.4.
-
J. Kedzierski, D. Boyd, P. Ronsheim, S. Zafar, J. Newbury, J. Ott, C. Cabral, Jr., M. Ieong, and W. Haensch, "Threshold voltage control in NiSi-gated MOSFETs through silicidation induced impurity segregation (SIIS)," in IEDM Tech. Dig., 2003, pp. 13.3.1-13.3.4.
-
-
-
-
3
-
-
33645465482
-
3Si fully silicided gates
-
Jan
-
3Si fully silicided gates," IEEE Electron Device Lett., vol. 27, no. 1, pp. 34-36, Jan. 2006.
-
(2006)
IEEE Electron Device Lett
, vol.27
, Issue.1
, pp. 34-36
-
-
Kittl, J.A.1
Pawlak, M.A.2
Lauwers, A.3
Demeurisse, C.4
Opsomer, K.5
Anil, K.G.6
Vrancken, C.7
van Dal, M.J.H.8
Veloso, A.9
Kubicek, S.10
Absil, P.11
Maex, K.12
Biesemans, S.13
-
5
-
-
34447260864
-
Dual workfunction Ni-silicide/HfSiON gate stacks by phase-controlled full silicidation technique for 45 nm-node LSTP and LOP devices
-
K. Takahashi, K. Manabe, T. Ikarashi, N. Ikarashi, T. Hase, T. Yoshihara, H. Watanabe, T. Tatsumi, and Y. Mochizuki, "Dual workfunction Ni-silicide/HfSiON gate stacks by phase-controlled full silicidation technique for 45 nm-node LSTP and LOP devices," in IEDM Tech. Dig., 2005, pp. 775-778.
-
(2005)
IEDM Tech. Dig
, pp. 775-778
-
-
Takahashi, K.1
Manabe, K.2
Ikarashi, T.3
Ikarashi, N.4
Hase, T.5
Yoshihara, T.6
Watanabe, H.7
Tatsumi, T.8
Mochizuki, Y.9
-
6
-
-
0001218385
-
Thin films of rare earth metal silicides
-
Aug
-
V. M. Koleshko, V. F. Belitsky, and A. A. Khodin, "Thin films of rare earth metal silicides," Thin Solid Films, vol. 141, no. 2, pp. 277-285, Aug. 1986.
-
(1986)
Thin Solid Films
, vol.141
, Issue.2
, pp. 277-285
-
-
Koleshko, V.M.1
Belitsky, V.F.2
Khodin, A.A.3
-
7
-
-
33644623928
-
Yb-doped Ni FUSI for the n-MOSFETs gate electrode application
-
Mar
-
J. D. Chen, H. Y. Yu, M. F. Le, D.-L. Kwong, M. J. H. van Dal, J. A. Kittl, A. Lauwers, P. Absil, M. Jurczak, and S. Biesemans, "Yb-doped Ni FUSI for the n-MOSFETs gate electrode application," IEEE Electron Device Lett., vol. 27, no. 3, pp. 160-162, Mar. 2006.
-
(2006)
IEEE Electron Device Lett
, vol.27
, Issue.3
, pp. 160-162
-
-
Chen, J.D.1
Yu, H.Y.2
Le, M.F.3
Kwong, D.-L.4
van Dal, M.J.H.5
Kittl, J.A.6
Lauwers, A.7
Absil, P.8
Jurczak, M.9
Biesemans, S.10
-
8
-
-
33644806622
-
Full silicidation of silicon gate electrode using nickel-terbium alloy for MOSFET applications
-
A. E. Lim, R. T. Lee, C. H. Tung, S. Tripathy, D. L. Kwong, and Y. C. Yeo, "Full silicidation of silicon gate electrode using nickel-terbium alloy for MOSFET applications," J. Electrochem. Soc., vol. 153, no. 4, pp. G337-G340, 2006.
-
(2006)
J. Electrochem. Soc
, vol.153
, Issue.4
-
-
Lim, A.E.1
Lee, R.T.2
Tung, C.H.3
Tripathy, S.4
Kwong, D.L.5
Yeo, Y.C.6
-
9
-
-
0001954222
-
Characterization of ultra-thin oxides using electrical C-V and I-V measurements
-
J. R. Hauser and K. Ahmed, "Characterization of ultra-thin oxides using electrical C-V and I-V measurements," in Proc. AIP Conf. 1998, vol. 449, pp. 235-239.
-
(1998)
Proc. AIP Conf
, vol.449
, pp. 235-239
-
-
Hauser, J.R.1
Ahmed, K.2
-
10
-
-
36149003066
-
Anisotropy of the electronic work function of metals
-
Nov
-
R. Smoluchowski, "Anisotropy of the electronic work function of metals," Phys. Rev., vol. 60, no. 9, pp. 661-674, Nov. 1941.
-
(1941)
Phys. Rev
, vol.60
, Issue.9
, pp. 661-674
-
-
Smoluchowski, R.1
-
11
-
-
4544267525
-
Physics in fermi level pinning at the poly Si/Hf-based high-k oxide interface
-
K. Shiraishi, K. Yamada, K. Tori, Y. Akasaka, K. Nakajima, M. Kohno, T. Chikyo, H. Kitajima, and T. Arikato, "Physics in fermi level pinning at the poly Si/Hf-based high-k oxide interface," in VLSI Symp. Tech. Dig., 2004, pp. 108-109.
-
(2004)
VLSI Symp. Tech. Dig
, pp. 108-109
-
-
Shiraishi, K.1
Yamada, K.2
Tori, K.3
Akasaka, Y.4
Nakajima, K.5
Kohno, M.6
Chikyo, T.7
Kitajima, H.8
Arikato, T.9
-
12
-
-
4944257396
-
Engineering chemically abrupt high-k metal oxide/silicon interface using an oxygen-gettering metal overlayer
-
Sep
-
H. Kim, P. C. McIntyre, C. Chui, K. C. Saraswat, and S. Stemmer, "Engineering chemically abrupt high-k metal oxide/silicon interface using an oxygen-gettering metal overlayer," J. Appl. Phys. vol. 96, no. 6, pp. 3467-3472, Sep. 2004.
-
(2004)
J. Appl. Phys
, vol.96
, Issue.6
, pp. 3467-3472
-
-
Kim, H.1
McIntyre, P.C.2
Chui, C.3
Saraswat, K.C.4
Stemmer, S.5
-
14
-
-
0034350481
-
3)/ GaAs interface: Structures and compositions
-
3)/ GaAs interface: Structures and compositions," J. Vac. Sci. Technol. B,Microelectron. Process. Phenom., vol. 18, no. 3, pp. 1688-1691, 2000.
-
(2000)
J. Vac. Sci. Technol. B,Microelectron. Process. Phenom
, vol.18
, Issue.3
, pp. 1688-1691
-
-
Hong, M.1
Kortan, A.R.2
Kwo, J.3
Mannaerts, J.P.4
Krajewski, J.J.5
Lu, Z.H.6
Heieh, K.C.7
Cheng, K.Y.8
-
15
-
-
0842266664
-
Nitrogen profile control by plasma nitridation technique for poly-Si gate HfSiON CMOSFET with excellent interface property and ultra-low leakage current
-
K. Sekine, S. Inumiya, M. Sato, A. Kaneko, K. Eguchi, and Y. Tsunashima, "Nitrogen profile control by plasma nitridation technique for poly-Si gate HfSiON CMOSFET with excellent interface property and ultra-low leakage current," in IEDM Tech. Dig., 2003, pp. 103-106.
-
(2003)
IEDM Tech. Dig
, pp. 103-106
-
-
Sekine, K.1
Inumiya, S.2
Sato, M.3
Kaneko, A.4
Eguchi, K.5
Tsunashima, Y.6
|