Area-efficient selective multi-threshold CMOS design methodology for standby leakage power reduction

Proceedings -Design, Automation and Test in Europe, DATE '05

Volumn I, Issue , 2005, Pages 646-647

  Kitahara, Takeshi ^a   Kawabe, Naoyuki ^a   Minami, Fimihiro ^a   Seta, Katsuhiro ^a   Furusawa, Toshiyuki ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC POWER DISTRIBUTION; LEAKAGE CURRENTS; NETWORKS (CIRCUITS); OPTIMIZATION; THRESHOLD VOLTAGE; TRANSISTORS;

CMOS DESIGN METHODOLOGY; LEAKAGE POWER REDUCTION; MULTI-THRESHOLD CMOS DESIGN METHODOLOGY; REGISTER TRANSFER LEVEL (RTL);

CMOS INTEGRATED CIRCUITS;

EID: 33646919151     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2005.68     Document Type: Conference Paper

References (4)

1. L.Wei et al., "Power Minimization by Simultaneous Dual-Vth Assignment and Gate-sizing", CICC, 2000.
2. K.Usami et al., "Automated Selective Multi-Threshold Design For Ultra-Low Standby Applications", ISLPED, 2002.
3. G.Uvieghara et al., "A Highly-Integrated 3G CDMA2000 IX Cellular Baseband Chip With GSM/AMPS/GPS/Bluetooth/ Multimedia Capabilities And ZIP RF Support", ISSCC, 2004.
4. http://www.sequencedesign.com/