A test structure for contact and via failure analysis in deep-submicrometer CMOS technologies

IEEE Transactions on Semiconductor Manufacturing

Volumn 19, Issue 1, 2006, Pages 57-65

  Cabrini, Alessandro ^a,b   Cantarelli, Daniele ^c,d,e   Cappelletti, Paolo ^c,f   Casiraghi, Roberto ^c   Maurelli, Alfonso ^c,g,h,i,j   Pasotti, Marco ^c   Rolandi, Pier Luigi ^a,c,k   Torelli, Guido ^a,b,l  

^a IEEE   (Italy)

^b UNIVERSITY OF PAVIA   (Italy)

^c STMICROELECTRONICS   (Italy)

^d Flash EEFROM Group

^e 256 Kb and 1 Mb Memory Devices Programs ^*

^f NVM Technologies

^g FTM RandD Nonvolatile Memory Technology Development Department

^h Embedded Flash Technology Integration International Research

ⁱ MEDEA + NEMESYS Project   (Algeria)

^j European Solid State Device Research Conference (ESSDERC)

^k Innovative Systems Design Group

^l Italian Association of Electrical and Electronics Engineers (AEI)   (Italy)

more..

Author keywords

Contacts; Interconnect; Reliability; Test structure; Vias; Yield

Indexed keywords

INTERCONNECT ELEMENTS; TEST STRUCTURE; VIAS;

ELECTRIC CONTACTS; ELECTRIC RESISTANCE; FAILURE ANALYSIS; RELIABILITY;

CMOS INTEGRATED CIRCUITS;

EID: 33144475037     PISSN: 08946507     EISSN: None     Source Type: Journal    
DOI: 10.1109/TSM.2005.863226     Document Type: Conference Paper

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