Architecture scalability of parallel vector computers with a shared memory

IEEE Transactions on Computers

Volumn 47, Issue 5, 1998, Pages 614-624

  Dekker, Eskil ^a,b  

^a IEEE   (Netherlands)

^b DELFT UNIVERSITY OF TECHNOLOGY   (Netherlands)

Author keywords

Architecture scalability; Parallel vector computers; Shared memory; Sustainable peak performance; Theoretical peak performance

Indexed keywords

EID: 33747731477     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.677257     Document Type: Article

References (29)

1. C.N. Arnold, "Methods for Performance Evaluation of Algorithms and Computers," Computers in Physics, vol. 4, no. 5, pp. 514-520, Sept./ Oct. 1990.
2. G. Bilardi and F.P. Preparata, "Horizons of Parallel Computation," J. Parallel and Distributed Computing, vol. 27, no. 2, pp. 172-182, June 1995.
3. G. Bell, "Ultracomputers: A Teraflop Before Its Time," Comm. ACM, vol. 35, no. 8, pp. 27-47, Aug. 1992.
4. V.E. Benes, Mathematical Theory of Connecting Networks and Telephone Traffic. New York: Academic Press, 1965.
5. C. Clos, "A Sudy of Non-Blocking Switching Networks," Bell System Technical J., vol. 32, pp. 406-424, Mar. 1953.
6. D.M. Dias and J.R. Jump, "Analysis and Simulation of Buffered Delta Networks," IEEE Trans. Computers, vol. 30, no. 4, pp. 273-282, Apr. 1981.
7. J. Ding and L.N. Bhuyan, "Finite Buffer Analysis of Multistage Interconnection Networks," IEEE Trans. Computers, vol. 43, no. 2, pp. 243-247, Feb. 1994.
8. J.J. Dongarra, "Performance of Various Computers Using Standard Linear Equations Software," Technical Report CS-89-85, Univ. of Tennessee and Oak Ridge Nat'l Laboratory, Nov. 1995.
9. J.J. Dongarra, "The LINPACK Benchmark: An Explanation," Lecture Notes in Computer Science, vol. 297, pp. 456-474. Berlin: Springer, 1988.
10. T.-Y. Feng, "A Survey of Interconnection Networks," Computer, vol. 14, no. 12, pp. 12-27, Dec. 1981.
11. G.H. Golub and C.F. Van Loan, Matrix Computations, second ed., chapter 3. Baltimore: The Johns Hopkins Univ. Press, 1989.
12. J.J. Hack, "Peak vs. Sustained Performance in Highly Concurrent Vector Machines," Computer, vol. 19, no. 9, pp. 11-19, Sept. 1986.
13. M.D. Hill, "What Is Scalability?" Computer Architecture News, vol. 18, no. 4, pp. 18-21, Dec. 1990.
14. R.W. Hockney, "Super-Computer Architecture," Infotech State of the Art Report: Future Systems 2, pp. 277-305. Maidenhead: Infotech, 1977.
15. K. Hwang, Advanced Computer Architecture: Parallelism, Scalability, Programmability, p. 338. New York: McGraw-Hill, 1993.
16. V. Kumar and A. Gupta, "Analysis of Scalability of Parallel Algorithms and Architectures: A Survey," Pros. Int'l Conf. Supercomputing, pp. 396-405, 1991.
17. D.H. Lawrie, "Access and Alignment of Data in an Array Processor," IEEE Trans. Computers, vol. 24, no. 12, pp. 1,145-1,155, Dec. 1975.
18. G.F. Lev, N. Pippenger, and L.G. Valiant, "A Fast Parallel Algorithm for Routing in Permutation Networks," IEEE Trans. Computers, vol. 30, no. 2, pp. 93-100, Feb. 1981.
19. Y. Mun and H.Y. Youn, "Performance Analysis of Finite Buffered Multistage Interconnection Networks," IEEE Trans. Computers, vol. 43, no. 2, pp. 153-162, Feb. 1994.
20. D. Nassimi and S. Sahni, "A Self-Routing Benes Network and Parallel Permutation Algorithms," IEEE Trans. Computers, vol. 30, no. 5, pp. 332-340, May 1981.
21. D. Nassimi and S. Sahni, "Parallel Algorithmsto Set-Up the Benes Permutation Network," Proc. Workshop Interconnection Networks for Parallel and Distributed Processing, pp. 70-71, 1980.
22. D. Nusbaum and A. Agarwal, "Scalability of Parallel Machines," Comm. ACM, vol. 34, no. 3, pp. 56-61, Mar. 1991.
23. J.H. Patel, "Performance of Processor-Memory Interconnections for Multiprocessors," IEEE Trans. Computers, vol. 30, no. 10, pp. 771-780, Oct. 1981.
24. C.S. Raghavendra and R.V. Boppana, "On Self-Routing in Benes and Shuffle-Exchange Networks," IEEE Trans. Computers, vol. 40, no. 9, pp. 1,057-1,064, Sept. 1991.
25. H.S. Stone, "Parallel Processing with the Perfect Shuffle," IEEE Trans. Computers, vol. 20, no. 2, pp. 153-161, Feb. 1971.
26. Y. Tamir and H.-C. Chi, "Symmetric Crossbar Arbiters for VLSI Communication Switches," IEEE Trans. Parallel and Distributed Systems, vol. 4, no. 1, pp. 13-27, Jan. 1993.
27. C.-L. Wu and T.-Y. Feng, "On a Class of Multistage Interconnection Networks," IEEE Trans. Computers, vol. 29, no. 8, pp. 694-702, Aug. 1980.
28. Y.-M. Yeh and T.-Y. Feng, "On a Class of Rearrangeable Networks," IEEE Trans. Computers, vol. 41, no. 11, pp. 1,361-1,379, Nov. 1992.
29. H.Y. Youn and Y. Mun, "On Multistage Interconnection Networks with Small Clock Cycles," IEEE Trans. Parallel and Distributed Systems, vol. 6, no. 1, pp. 86-93, Jan. 1995.