A model of fringing fields in short-channel planar and triple-gate SOI MOSFETs

IEEE Transactions on Electron Devices

Volumn 54, Issue 6, 2007, Pages 1366-1375

  Ernst, Thomas ^a   Ritzenthaler, Romain ^a,b   Faynot, Oliver ^a   Cristoloveanu, Sorin ^b  

^a CEA LETI   (France)

^b MINATEC   (France)

Author keywords

Electrostatic analysis; Interface phenomena; MOS devices; Silicon on insulator (SOI) technology

Indexed keywords

CONFORMAL MAPPING; MATHEMATICAL MODELS; OPTIMIZATION; SILICON ON INSULATOR TECHNOLOGY; SUBSTRATES; THRESHOLD VOLTAGE; TWO DIMENSIONAL;

ELECTROSTATIC ANALYSIS; SHORT-CHANNEL EFFECTS;

MOSFET DEVICES;

EID: 34249892435     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2007.895241     Document Type: Article

References (18)

1. S. Cristoloveanu and S. S. Li, Electrical Characterization of Silicon-On-Insulator Materials and Devices. Boston, MA: Kluwer, 1995.
2. R. Koh, "Buried layer engineering to reduce the drain-induced barrier lowering of sub-0.05 μm SOI-MOSFET," Jpn. J. Appl. Phys., vol. 38, no. 4B, pp. 2294-2299, Apr. 1999.
3. T. Ernst and S. Cristoloveanu, "Buried oxide fringing capacitance: A new physical model and its implication on SOI device scaling and architecture," in Proc. IEEE Int. SOI Conf., 1999, pp. 38-39.
4. P. C. Yeh and J. G. Fossum, "Physical subthreshold MOSFET modeling applied to viable design of deep-submicrometer fully depleted SOI low-voltage CMOS technology," IEEE Trans. Electron Devices, vol. 42, no. 9, pp. 1605-1613, Sep. 1995.
5. H.-O. Joachim, Y. Yamagushi, K. Ishikawa, Y. Inoue, and T. Nishimura, "Simulation and two-dimensional analytical modeling of subthreshold slope in ultrathin-film SOI MOSFET's down to 0.1 μm gate length," IEEE Trans. Electron Devices, vol. 40, no. 10, pp. 1812-1817, Oct. 1993.
6. J. A. Martino, L. Lauwers, J. P. Colinge, and K. de Meyer, "Model for the potential drop in the silicon substrate for thin-film SOI MOSFETs," Electron. Lett., vol. 26, no. 18, pp. 1462-1464, Aug. 1990.
7. Z.-H. Liu, C. Hu, J.-H. Huang, T. Y. Chan, M.-C. Jeng, P. K. Ko, and Y. C. Cheng, "Threshold voltage model for deep-submicrometer MOSFETs," IEEE Trans. Electron Devices, vol. 40, no. 1, pp. 86-95, Jan. 1993.
8. S. R. Banna, P. C. H. Chan, M. Chan, and P. K. Ko, "A physically based compact device model for fully depleted and nearly fully depleted SOI MOSFET," IEEE Trans. Electron Devices, vol. 43, no. 11, pp. 1914-1923, Nov. 1996.
9. G. F. Niu, R. M. M. Chen, and G. Ruan, "Comparisons and extension of recent surface potential models for fully depleted short-channel SOI MOSFET's," IEEE Trans. Electron Devices, vol. 43, no. 11, pp. 2034-2037, Nov. 1996.
10. T. Ernst, C. Tinella, C. Raynaud, and S. Cristoloveanu, "Fringing fields in sub-0.1 μm FD SOI MOSFETs: Optimization of the device architectures," Solid State Electron., vol. 46, no. 463, pp. 373-378, Mar. 2002.
11. G. Strang, Introduction to Applied Mathematics. Wellesley, (MA), USAMA: Wellesley-Cambridge Press, 1986.
12. E. Carlsson and S. Gevorgian, "Conformal mapping of the field and charge distributions in multilayers substrates CPW's," IEEE Trans. Microw. Theory Tech., vol. 47, no. 8, pp. 1544-1552, Aug. 1999.
13. R. Koh, H. Kato, and H. Matsumoto, "Capacitance network model of the short channel effect for 0.1 μm fully depleted SOI MOSFET," Jpn. J. Appl. Phys., vol. 35, no. (2B), pp. 996-1000, 1996.
14. S.-M. Sze, Physics of Semiconductor Devices, 2nd ed. Hoboken, NJ: Wiley, 1981.
15. B. Doyle, B. Boyanov, S. Datta, M. Doczy, S. Hareland, B. Jin, J. Kavalieros, T. Linton, R. Rios, and R. Chau, "Tri-gate fully depleted CMOS transistors: Fabrication, design and layout," in VLSI 2003 Tech. Dig. Symp., 2003, pp. 132-133.
16. F. Daugé, J. Pretet, S. Cristoloveanu, A. Vandooren, L. Mathew, J. Jomaah, and B.-Y. Nguyen, "Coupling effects and channel separation in FinFETs," Solid State Electron., vol. 48, no. 4, pp. 535-542, Apr. 2004.
17. M. Gaillardin, P. Paillet, V. Ferlet-Cavrois, S. Cristoloveanu, O. Faynot, and C. Jahan, "High tolerance to total ionizing dose of Ω-shaped gate field-effect transistors," Appl. Phys. Lett., vol. 88, no. 4, p. 223 511, 2006.
18. R. Ritzenthaler, S. Cristoloveanu, O. Faynot, C. Jahan, A. Kuriyama, L. Brevard, and S. Deleonibus, "Lateral coupling and immunity to substrate effect in ΩFET devices," Solid State Electron., vol. 50, no. 4, pp. 558-565, Apr. 2006.