A power-efficient two-channel time-interleaved Σ△ modulator for broadband applications

IEEE Journal of Solid-State Circuits

Volumn 42, Issue 6, 2007, Pages 1206-1215

  Lee, Kye Shin ^a,b   Kwon, Sunwoo ^a,c   Maloberti, Franco ^a,d  

^a IEEE   (United States)

^b TEXAS INSTRUMENTS   (United States)

^c Oregon State University   (United States)

^d UNIVERSITY OF PAVIA   (Italy)

Author keywords

Channel mismatch; Effective clock frequency; Sigma delta ( ) modulator; Signal bandwidth; Single integrator channel; Time interleaved (TI)

Indexed keywords

CHANNEL MISMATCH; CMOS TECHNOLOGY; EFFECTIVE CLOCK FREQUENCY; SIGMA-DELTA MODULATORS; SIGNAL BANDWIDTH; SINGLE INTEGRATOR CHANNELS; TIME-INTERLEAVED (TI);

BANDWIDTH; CAPACITORS; CHANNEL ESTIMATION; CMOS INTEGRATED CIRCUITS; ELECTRIC POWER UTILIZATION; ENERGY EFFICIENCY; MODULATORS; ROBUST CONTROL;

BROADBAND NETWORKS;

EID: 34249799939     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2007.897151     Document Type: Article

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