A 33 mW 14 b 2.5 Msample/s ΣΔ A/D converter in 0.25 μm digital CMOS

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2002, Pages 316-317+469+305

  Reutemann, Robert ^a   Balmelli, Pio ^a   Huang, Qiuting ^a  

^a ETH ZURICH   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; ATTENUATION; CAPACITORS; CMOS INTEGRATED CIRCUITS; FIR FILTERS; SIGNAL FILTERING AND PREDICTION; SIGNAL TO NOISE RATIO; THERMAL NOISE; TRANSFER FUNCTIONS; WIRELESS TELECOMMUNICATION SYSTEMS;

CROSS-COUPLED CAPACITORS;

ANALOG TO DIGITAL CONVERSION;

EID: 0036105697     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. A 3.3-V, 15-bit, delta-sigma ADC with a signal bandwidth of 1.1 MHz for ADSL applications
2. 14-bit 2.2-MS/s sigma-delta ADC's
3. A 90-dB SNR 2.5-MHz output-rate ADC using cascaded multibit delta-sigma modulation at 8x oversampling ratio
4. A 2.5 V broadband multi-bit ΣΔ modulator with 95 dB dynamic range
5. A 50-mW 14-bit 2.5-MS/s ΣΔ modulator in a 0.25 μm digital CMOS technology