New insights on "Capacitorless" floating-body DRAM cells

IEEE Electron Device Letters

Volumn 28, Issue 6, 2007, Pages 513-516

  Fossum, Jerry G ^a   Lu, Zhichao ^a   Trivedi, Vishal P ^b  

^a J Crayton Pruitt Family Department of Biomedical Engineering   (United States)

^b FREESCALE SEMICONDUCTOR INC   (United States)

Author keywords

Body capacitance; Double gate (DG) MOSFETs; Floating body effects; Independent gate (IG) FinFET; P n junction; Silicon on insulator (SOI) MOSFETs

Indexed keywords

CAPACITANCE; COMPUTER SIMULATION; GATES (TRANSISTOR); SEMICONDUCTOR JUNCTIONS; SILICON ON INSULATOR TECHNOLOGY;

BODY CAPACITANCE; FLOATING-BODY EFFECTS;

MOSFET DEVICES;

EID: 34249787305     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2007.896883     Document Type: Article

References (13)

1. S. Okhonin et al., "A SOI capacitor-less 1T-DRAM concept," in Proc. IEEE Int. SOI Conf., Oct. 2001, pp. 153-154.
2. R. Ranica et al., "A capacitor-less DRAM cell on 75 nm gate length, 16 nm thin fully depleted SOI device for high density embedded memories," in IEDM Tech. Dig., Dec. 2004, pp. 277-280.
3. S. Okhonin et al., "FinFET based zero-capacitor DRAM (Z-RAM) cell for sub 45 nm memory generations," in Proc. IC-MTD, May 2005, pp. 63-65.
4. E. Yoshida, T. Miyashita, and T. Tanaka, "A study of highly scalable DGFinDRAM," IEEE Electron Device Lett., vol. 26, no. 9, pp. 655-657, Sep. 2005.
5. T. Shino et al., "Operation voltage dependence of memory cell characteristics in fully depleted floating-body cell," IEEE Trans. Electron Devices, vol. 52, no. 10, pp. 2220-2226, Oct. 2005.
6. E. Yoshida and T. Tenaka, "A capacitorless 1T-DRAM technology using gate-induced drain-leakage (GIDL) current for low-power and highspeed embedded memory," IEEE Trans. Electron Devices, vol. 53, no. 4, pp. 692-697, Apr. 2006.
7. T. Shino et al., "Floating body RAM technology and its scalability to 32 nm node and beyond," in IEDM Tech. Dig., Dec. 2006, pp. 569-572.
8. I. Ban et al., "Floating body cell with independently-controlled double gates for high density memory," in IEDM Tech. Dig., Dec. 2006, pp. 573-576.
9. S. Krishnan and J. G. Fossum, "Grasping SOI floating-body effects," IEEE Circuits Devices Mag., vol. 14, no. 4, pp. 32-37, Jul. 1998.
10. Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices. Cambridge, U.K.: Cambridge Univ. Press, 1998.
11. H.-K. Lim and J. G. Fossum, "Threshold voltage of thin-film silicon-on-insulator (SOI) MOSFETs," IEEE Trans. Electron Devices vol. ED-30, no. 10, pp. 1244-1251, Oct. 1983.
12. Taurus-2006 User's Manual, Synopsys, Inc., Durham, NC, 2006.
13. S.-H. Kim, J. G. Fossum, and V. P. Trivedi, "Bulk inversion in FinFETs and implied insights on effective gate width," IEEE Trans. Electron Devices, vol. 52, no. 9, pp. 1993-1997, Sep. 2005.