The exact channel density and compound design for generic universal switch blocks

ACM Transactions on Design Automation of Electronic Systems

Volumn 12, Issue 2, 2007, Pages

  Fan, Hongbing ^a   Liu, Jiping ^b   Wu, Yu Liang ^c   Cheung, Chak Chung ^d  

^a WILFRID LAURIER UNIVERSITY   (Canada)

^b UNIVERSITY OF LETHBRIDGE   (Canada)

^c CHINESE UNIVERSITY OF HONG KONG   (Hong Kong)

^d IMPERIAL COLLEGE LONDON   (United Kingdom)

Author keywords

FPGA architecture; Routing algorithm; Universal switch block

Indexed keywords

FPGA ARCHITECTURE; UNIVERSAL SWITCH BLOCK;

CARRIER CONCENTRATION; COMPUTER AIDED DESIGN; ELECTRONIC EQUIPMENT MANUFACTURE; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); NUMBER THEORY; PROBLEM SOLVING; ROUTING ALGORITHMS;

SWITCHING SYSTEMS;

EID: 34248327916     PISSN: 10844309     EISSN: 15577309     Source Type: Journal    
DOI: 10.1145/1230800.1230811     Document Type: Article

References (16)

1. BETZ, V. AND ROSE, J. 1997. A new packing, placement and routing tool for FPGA research. In Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications. 213-222. http://www.eecg.toronto.edu/~jayar/software.html.
2. BETZ, V., ROSE, J., AND MORQUARDT, A. 1999. Architecture and CAD for Deep-Submicron FPGAs. Kluwer Academic, Boston, MA.
3. BROWN, S; FRANCINE, R. J., ROSE, J., AND VRANESIC, Z. G. 1992. Field-Programmable Gate Arrays. Kluwer Academic, Boston, MA.
4. CHANG, Y. W., WONG, D. F., AND WONG, C. K. 1996. Universal switch models for FPGA. ACM Trans. Des. Autom. Electron. Syst. 1, 1 (Jan.), 80-101.
5. FAN, H., LIU, G., AND LIU, J. 2006. Minimal regular 2-graphs and applications. Sci. China Series A Math. 49, 158-172.
6. FAN, H., LIU, J., AND WU, Y. L. 2000. General models for optimum arbitrary-dimension FPGA switch box designs. In Proceedings of the IEEE International Conference on Computer-Aided Design (ICCAD) (Nov.). 93-98.
7. FAN, H., LIU, J., WU, Y. L., AND CHEUNG, C. C. 2001. On optimum switch box designs for 2-D FPGAs. In Proceedings of the IEEE/ACM Design Automation Conference (DAC) (Jun.). 203-208.
8. FAN, H., LIU, J., WU, Y. L., AND WONG, C. K. 2002a. Reduction design for generic universal switch blocks. ACM Trans. Des. Autom. Electron. Syst. 7, 4 (Dec.), 526-546.
9. FAN, H., WU, Y. L., AND CHANG, Y. W. 2002b. Comment on general universal switch blocks. IEEE Trans. Comput. 51, 1 (Jan.), 93-95.
10. LEMIEUX, G. AND LEWIS, D. 2003. Design of Interconnection Networks for Programmable Logic. Kluewer Academic, Boston, MA.
11. LOVASZ, L. AND PUMMER, M. D. 1986. Matching Theory. Elsevier Science, New York.
12. PAN, J. F., WU, Y. L., YAN, G., AND WONG, C. K. 1998. On the optimal four-way switch box routing structures of FPGA greedy routing architectures. Integration VLSI J. 25, 137-159.
13. ROSE, J. AND BROWN, S. 1991. Flexibility of interconnection structures for field-programmable gate arrays. IEEE J. Solid-State Circ. 26, 3, 277-282.
14. SHYU, M., WU, G. M., CHANG, Y. D., AND CHANG, Y. W. 2000. Generic universal switch blocks. IEEE Trans. Comput., (Apr.), 348-359.
15. WILTON, S. J. E. 1997. Architecture and algorithms for field-programmable gate arrays with embedded memory. Ph.D. thesis, University of Toronto.
16. WU, Y. L., TSUKIYAMA, S., AND MAREK-SADOWSKA, M. 1996. Graph based analysis of 2-D FPGA routing. IEEE Trans. Camput.-Aided Des. 15, 1, 33-44.