On the optimal four-way switch box routing structures of FPGA greedy routing architectures

Integration, the VLSI Journal

Volumn 25, Issue 2, 1998, Pages 137-159

  Pan, Jiaofeng ^a   Wu, Yu Liang ^a,d   Wong, C K ^a,c   Yan, Guiying ^b  

^a CHINESE UNIVERSITY OF HONG KONG   (Hong Kong)

^b INSTITUTE OF APPLIED MATHEMATICS   (China)

^c IBM T J WATSON RESEARCH CENTER   (United States)

^d UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

FPGA routing architecture

Indexed keywords

COMPUTATIONAL COMPLEXITY; COMPUTER ARCHITECTURE; CONGESTION CONTROL (COMMUNICATION); DATA COMMUNICATION SYSTEMS; ELECTRIC SWITCHES; MICROPROCESSOR CHIPS; OPTIMIZATION; POLYNOMIALS;

GREEDY ROUTING ARCHITECTURE (GRA); OPTIMAL FOUR-WAY SWITCH BOX ROUTING STRUCTURES;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 0032203974     PISSN: 01679260     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0167-9260(98)00011-X     Document Type: Article

References (12)

1. Y.L. Wu, D. Chang, M. Marek-Sadowska, S. Tsukiyama, Not necessarily more switches more routability, Proc. ASP-DAC, 1997, pp. 579-584.
2. Y.L. Wu, M. Tsukiyama, Marek-Sadowska, Graph based analysis of 2-D FPGA routing, IEEE Trans. Comput. Aided Des. 15 (1) (1996) 33-44.
3. Y.L. Wu, D. Chang, On the NP-completeness of regular 2-D FPGA routing architectures and a novel solution, Proc. Int. Conf. On CAD, 1994, pp. 362-366.
4. "The Programmable Logic Data Book," Xilinx, 1994.
5. M. Sarrafzadeh, C.K. Wong, An Introduction To VLSI Physical Design, McGraw-Hill, 1996.
6. Yao-wen Chang, Routing architectures and algorithms for field programmable gate arrays, Ph.D Thesis, Department of Computer Science, University of Texas, Austin, 1996.
7. S. Brown, R. Francis, J. Rose, Z.G. Vranesic, Field Programmable Gate Arrays, Kluwer Academic Publishers, Dordrecht, 1992.
8. V.C. Chan, D.B. Lewis, Area-speed tradeoffs for hierarchical field-programmable gate arrays, Proc. Int. Symp. on FPGAs, 1996, pp. 51-57.
9. Y.L. Wu, Malgorzata Marek-Sadowska, Graph based Analysis of FPGA Routing, Proc. EURO-DAC with EURO-VHDL, 1993, pp. 104-109.
10. R. Amerson, R. Carter, W. Culbertson, P. Kuekes, G. Snider, Teramac-configurable custom computing, Proc. IEEE Symp. on FPGAs for Custom Computing Machines, 1995, pp. 32-38.
11. R. Amerson, R. Carter, W. Culbertson, P. Kuekes, G. Snider, Plasma: an FPGA for million gate systems, Proc. Int. Symp. on FPGAs, 1996, pp. 10-16.
12. L. Lovasz, M.D. Plummer, Matching Theory, Elservier, Amsterdam, 1986.